staging: et131x: move et1310_rx.h contents into et131x.c
Move et1310_rx.h contents into et131x.c and delete et1310_rx.h Signed-off-by: Mark Einon <mark.einon@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Einon
Greg Kroah-Hartman
Родитель
1c1c1b5fda
Коммит
562550b02b
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@ -1,243 +0,0 @@
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/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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* Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
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*
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*------------------------------------------------------------------------------
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*
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* et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
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* reception.
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#ifndef __ET1310_RX_H__
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#define __ET1310_RX_H__
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#define USE_FBR0 true
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#ifdef USE_FBR0
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/* #define FBR0_BUFFER_SIZE 256 */
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#endif
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/* #define FBR1_BUFFER_SIZE 2048 */
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#define FBR_CHUNKS 32
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#define MAX_DESC_PER_RING_RX 1024
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/* number of RFDs - default and min */
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#ifdef USE_FBR0
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#define RFD_LOW_WATER_MARK 40
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#define NIC_MIN_NUM_RFD 64
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#define NIC_DEFAULT_NUM_RFD 1024
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#else
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#define RFD_LOW_WATER_MARK 20
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#define NIC_MIN_NUM_RFD 64
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#define NIC_DEFAULT_NUM_RFD 256
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#endif
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#define NUM_PACKETS_HANDLED 256
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#define ALCATEL_BAD_STATUS 0xe47f0000
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#define ALCATEL_MULTICAST_PKT 0x01000000
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#define ALCATEL_BROADCAST_PKT 0x02000000
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/* typedefs for Free Buffer Descriptors */
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struct fbr_desc {
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u32 addr_lo;
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u32 addr_hi;
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u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
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};
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/* Packet Status Ring Descriptors
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*
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* Word 0:
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*
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* top 16 bits are from the Alcatel Status Word as enumerated in
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* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
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*
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* 0: hp hash pass
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* 1: ipa IP checksum assist
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* 2: ipp IP checksum pass
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* 3: tcpa TCP checksum assist
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* 4: tcpp TCP checksum pass
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* 5: wol WOL Event
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* 6: rxmac_error RXMAC Error Indicator
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* 7: drop Drop packet
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* 8: ft Frame Truncated
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* 9: jp Jumbo Packet
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* 10: vp VLAN Packet
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* 11-15: unused
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* 16: asw_prev_pkt_dropped e.g. IFG too small on previous
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* 17: asw_RX_DV_event short receive event detected
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* 18: asw_false_carrier_event bad carrier since last good packet
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* 19: asw_code_err one or more nibbles signalled as errors
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* 20: asw_CRC_err CRC error
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* 21: asw_len_chk_err frame length field incorrect
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* 22: asw_too_long frame length > 1518 bytes
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* 23: asw_OK valid CRC + no code error
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* 24: asw_multicast has a multicast address
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* 25: asw_broadcast has a broadcast address
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* 26: asw_dribble_nibble spurious bits after EOP
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* 27: asw_control_frame is a control frame
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* 28: asw_pause_frame is a pause frame
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* 29: asw_unsupported_op unsupported OP code
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* 30: asw_VLAN_tag VLAN tag detected
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* 31: asw_long_evt Rx long event
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*
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* Word 1:
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* 0-15: length length in bytes
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* 16-25: bi Buffer Index
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* 26-27: ri Ring Index
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* 28-31: reserved
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*/
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struct pkt_stat_desc {
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u32 word0;
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u32 word1;
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};
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/* Typedefs for the RX DMA status word */
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/*
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* rx status word 0 holds part of the status bits of the Rx DMA engine
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* that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
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* which contains the Free Buffer ring 0 and 1 available offset.
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*
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* bit 0-9 FBR1 offset
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* bit 10 Wrap flag for FBR1
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* bit 16-25 FBR0 offset
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* bit 26 Wrap flag for FBR0
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*/
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/*
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* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
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* that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
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* which contains the Packet Status Ring available offset.
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*
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* bit 0-15 reserved
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* bit 16-27 PSRoffset
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* bit 28 PSRwrap
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* bit 29-31 unused
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*/
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/*
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* struct rx_status_block is a structure representing the status of the Rx
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* DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
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*/
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struct rx_status_block {
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u32 word0;
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u32 word1;
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};
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/*
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* Structure for look-up table holding free buffer ring pointers
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*/
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struct fbr_lookup {
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void *virt[MAX_DESC_PER_RING_RX];
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void *buffer1[MAX_DESC_PER_RING_RX];
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void *buffer2[MAX_DESC_PER_RING_RX];
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u32 bus_high[MAX_DESC_PER_RING_RX];
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u32 bus_low[MAX_DESC_PER_RING_RX];
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};
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/*
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* struct rx_ring is the sructure representing the adaptor's local
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* reference(s) to the rings
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*/
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struct rx_ring {
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#ifdef USE_FBR0
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void *fbr0_ring_virtaddr;
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dma_addr_t fbr0_ring_physaddr;
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void *fbr0_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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dma_addr_t fbr0_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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uint64_t fbr0_real_physaddr;
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uint64_t fbr0_offset;
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u32 local_fbr0_full;
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u32 fbr0_num_entries;
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u32 fbr0_buffsize;
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#endif
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void *fbr1_ring_virtaddr;
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dma_addr_t fbr1_ring_physaddr;
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void *fbr1_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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dma_addr_t fbr1_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
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uint64_t fbr1_real_physaddr;
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uint64_t fbr1_offset;
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struct fbr_lookup *fbr[2]; /* One per ring */
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u32 local_fbr1_full;
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u32 fbr1_num_entries;
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u32 fbr1_buffsize;
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void *ps_ring_virtaddr;
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dma_addr_t ps_ring_physaddr;
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u32 local_psr_full;
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u32 psr_num_entries;
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struct rx_status_block *rx_status_block;
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dma_addr_t rx_status_bus;
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struct list_head recv_buff_pool;
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/* RECV */
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struct list_head recv_list;
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u32 num_ready_recv;
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u32 num_rfd;
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bool unfinished_receives;
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struct list_head recv_packet_pool;
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/* lookaside lists */
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struct kmem_cache *recv_lookaside;
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};
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#endif /* __ET1310_RX_H__ */
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@ -82,7 +82,6 @@
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#include <linux/phy.h>
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#include "et1310_tx.h"
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#include "et1310_rx.h"
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#include "et131x.h"
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MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
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@ -186,6 +185,186 @@ MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
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#define PARM_TX_NUM_BUFS_DEF 4
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#define PARM_DMA_CACHE_DEF 0
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/* RX defines */
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#define USE_FBR0 true
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#ifdef USE_FBR0
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/* #define FBR0_BUFFER_SIZE 256 */
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#endif
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/* #define FBR1_BUFFER_SIZE 2048 */
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#define FBR_CHUNKS 32
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#define MAX_DESC_PER_RING_RX 1024
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/* number of RFDs - default and min */
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#ifdef USE_FBR0
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#define RFD_LOW_WATER_MARK 40
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#define NIC_MIN_NUM_RFD 64
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#define NIC_DEFAULT_NUM_RFD 1024
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#else
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#define RFD_LOW_WATER_MARK 20
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#define NIC_MIN_NUM_RFD 64
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#define NIC_DEFAULT_NUM_RFD 256
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#endif
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#define NUM_PACKETS_HANDLED 256
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#define ALCATEL_BAD_STATUS 0xe47f0000
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#define ALCATEL_MULTICAST_PKT 0x01000000
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#define ALCATEL_BROADCAST_PKT 0x02000000
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/* typedefs for Free Buffer Descriptors */
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struct fbr_desc {
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u32 addr_lo;
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u32 addr_hi;
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u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
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};
|
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|
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/* Packet Status Ring Descriptors
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*
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* Word 0:
|
||||
*
|
||||
* top 16 bits are from the Alcatel Status Word as enumerated in
|
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* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
|
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*
|
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* 0: hp hash pass
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* 1: ipa IP checksum assist
|
||||
* 2: ipp IP checksum pass
|
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* 3: tcpa TCP checksum assist
|
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* 4: tcpp TCP checksum pass
|
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* 5: wol WOL Event
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* 6: rxmac_error RXMAC Error Indicator
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* 7: drop Drop packet
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* 8: ft Frame Truncated
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* 9: jp Jumbo Packet
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* 10: vp VLAN Packet
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* 11-15: unused
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* 16: asw_prev_pkt_dropped e.g. IFG too small on previous
|
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* 17: asw_RX_DV_event short receive event detected
|
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* 18: asw_false_carrier_event bad carrier since last good packet
|
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* 19: asw_code_err one or more nibbles signalled as errors
|
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* 20: asw_CRC_err CRC error
|
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* 21: asw_len_chk_err frame length field incorrect
|
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* 22: asw_too_long frame length > 1518 bytes
|
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* 23: asw_OK valid CRC + no code error
|
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* 24: asw_multicast has a multicast address
|
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* 25: asw_broadcast has a broadcast address
|
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* 26: asw_dribble_nibble spurious bits after EOP
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* 27: asw_control_frame is a control frame
|
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* 28: asw_pause_frame is a pause frame
|
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* 29: asw_unsupported_op unsupported OP code
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* 30: asw_VLAN_tag VLAN tag detected
|
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* 31: asw_long_evt Rx long event
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*
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* Word 1:
|
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* 0-15: length length in bytes
|
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* 16-25: bi Buffer Index
|
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* 26-27: ri Ring Index
|
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* 28-31: reserved
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*/
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struct pkt_stat_desc {
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u32 word0;
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u32 word1;
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};
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/* Typedefs for the RX DMA status word */
|
||||
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||||
/*
|
||||
* rx status word 0 holds part of the status bits of the Rx DMA engine
|
||||
* that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
|
||||
* which contains the Free Buffer ring 0 and 1 available offset.
|
||||
*
|
||||
* bit 0-9 FBR1 offset
|
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* bit 10 Wrap flag for FBR1
|
||||
* bit 16-25 FBR0 offset
|
||||
* bit 26 Wrap flag for FBR0
|
||||
*/
|
||||
|
||||
/*
|
||||
* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
|
||||
* that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
|
||||
* which contains the Packet Status Ring available offset.
|
||||
*
|
||||
* bit 0-15 reserved
|
||||
* bit 16-27 PSRoffset
|
||||
* bit 28 PSRwrap
|
||||
* bit 29-31 unused
|
||||
*/
|
||||
|
||||
/*
|
||||
* struct rx_status_block is a structure representing the status of the Rx
|
||||
* DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
|
||||
*/
|
||||
struct rx_status_block {
|
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u32 word0;
|
||||
u32 word1;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for look-up table holding free buffer ring pointers
|
||||
*/
|
||||
struct fbr_lookup {
|
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void *virt[MAX_DESC_PER_RING_RX];
|
||||
void *buffer1[MAX_DESC_PER_RING_RX];
|
||||
void *buffer2[MAX_DESC_PER_RING_RX];
|
||||
u32 bus_high[MAX_DESC_PER_RING_RX];
|
||||
u32 bus_low[MAX_DESC_PER_RING_RX];
|
||||
};
|
||||
|
||||
/*
|
||||
* struct rx_ring is the sructure representing the adaptor's local
|
||||
* reference(s) to the rings
|
||||
*/
|
||||
struct rx_ring {
|
||||
#ifdef USE_FBR0
|
||||
void *fbr0_ring_virtaddr;
|
||||
dma_addr_t fbr0_ring_physaddr;
|
||||
void *fbr0_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
|
||||
dma_addr_t fbr0_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
|
||||
uint64_t fbr0_real_physaddr;
|
||||
uint64_t fbr0_offset;
|
||||
u32 local_fbr0_full;
|
||||
u32 fbr0_num_entries;
|
||||
u32 fbr0_buffsize;
|
||||
#endif
|
||||
void *fbr1_ring_virtaddr;
|
||||
dma_addr_t fbr1_ring_physaddr;
|
||||
void *fbr1_mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
|
||||
dma_addr_t fbr1_mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
|
||||
uint64_t fbr1_real_physaddr;
|
||||
uint64_t fbr1_offset;
|
||||
struct fbr_lookup *fbr[2]; /* One per ring */
|
||||
u32 local_fbr1_full;
|
||||
u32 fbr1_num_entries;
|
||||
u32 fbr1_buffsize;
|
||||
|
||||
void *ps_ring_virtaddr;
|
||||
dma_addr_t ps_ring_physaddr;
|
||||
u32 local_psr_full;
|
||||
u32 psr_num_entries;
|
||||
|
||||
struct rx_status_block *rx_status_block;
|
||||
dma_addr_t rx_status_bus;
|
||||
|
||||
struct list_head recv_buff_pool;
|
||||
|
||||
/* RECV */
|
||||
struct list_head recv_list;
|
||||
u32 num_ready_recv;
|
||||
|
||||
u32 num_rfd;
|
||||
|
||||
bool unfinished_receives;
|
||||
|
||||
struct list_head recv_packet_pool;
|
||||
|
||||
/* lookaside lists */
|
||||
struct kmem_cache *recv_lookaside;
|
||||
};
|
||||
|
||||
/* ADAPTER defines */
|
||||
/*
|
||||
* Do not change these values: if changed, then change also in respective
|
||||
|
|
|
|||
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