ARM: at91: pm: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
As already explained for pm_suspend.S, the DDRSDR controller fails to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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@ -241,12 +241,27 @@ static void at91_ddr_standby(void)
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1 = 0;
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u32 mdr, saved_mdr0, saved_mdr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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/* LPDDR1 --> force DDR2 mode during self-refresh */
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saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
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if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
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mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
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mdr |= AT91_DDRSDRC_MD_DDR2;
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at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
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}
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if (pm_data.ramc[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
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if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
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mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
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mdr |= AT91_DDRSDRC_MD_DDR2;
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at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
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}
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}
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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@ -260,10 +275,13 @@ static void at91_ddr_standby(void)
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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if (pm_data.ramc[1])
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if (pm_data.ramc[1]) {
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at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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}
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static void sama5d3_ddr_standby(void)
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{
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