clk: bcm: rpi: Remove the quirks for the CPU clock
The CPU clock has had so far a bunch of quirks to expose the clock tree properly, but since we reverted to exposing them through the MMIO driver, we can remove that code from the firmware driver. Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/acdf820c2f78a25dd7480a0c018b8b387acd013e.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Maxime Ripard
Stephen Boyd
Родитель
0d46fafc03
Коммит
56643d9ad2
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@ -56,14 +56,6 @@ static char *rpi_firmware_clk_names[] = {
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#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
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#define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1)
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/*
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* Even though the firmware interface alters 'pllb' the frequencies are
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* provided as per 'pllb_arm'. We need to scale before passing them trough.
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*/
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#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE 2
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#define A2W_PLL_FRAC_BITS 20
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struct raspberrypi_clk {
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struct device *dev;
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struct rpi_firmware *firmware;
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@ -152,13 +144,6 @@ static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
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return val;
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}
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static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return raspberrypi_fw_get_rate(hw, parent_rate) *
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RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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}
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static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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@ -177,142 +162,6 @@ static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
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return ret;
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}
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static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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return raspberrypi_fw_set_rate(hw, new_rate, parent_rate);
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}
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/*
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* Sadly there is no firmware rate rounding interface. We borrowed it from
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* clk-bcm2835.
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*/
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static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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u64 div, final_rate;
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u32 ndiv, fdiv;
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/* We can't use req->rate directly as it would overflow */
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final_rate = clamp(req->rate, req->min_rate, req->max_rate);
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div = (u64)final_rate << A2W_PLL_FRAC_BITS;
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do_div(div, req->best_parent_rate);
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ndiv = div >> A2W_PLL_FRAC_BITS;
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fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
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final_rate = ((u64)req->best_parent_rate *
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((ndiv << A2W_PLL_FRAC_BITS) + fdiv));
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req->rate = final_rate >> A2W_PLL_FRAC_BITS;
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return 0;
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}
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static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
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.is_prepared = raspberrypi_fw_is_prepared,
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.recalc_rate = raspberrypi_fw_pll_get_rate,
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.set_rate = raspberrypi_fw_pll_set_rate,
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.determine_rate = raspberrypi_pll_determine_rate,
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};
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static struct clk_hw *raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
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{
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struct raspberrypi_clk_data *data;
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struct clk_init_data init = {};
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u32 min_rate = 0, max_rate = 0;
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int ret;
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data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return ERR_PTR(-ENOMEM);
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data->rpi = rpi;
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data->id = RPI_FIRMWARE_ARM_CLK_ID;
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/* All of the PLLs derive from the external oscillator. */
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init.parent_names = (const char *[]){ "osc" };
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init.num_parents = 1;
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init.name = "pllb";
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init.ops = &raspberrypi_firmware_pll_clk_ops;
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init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
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/* Get min & max rates set by the firmware */
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ret = raspberrypi_clock_property(rpi->firmware, data,
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RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
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&min_rate);
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if (ret) {
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dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
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init.name, ret);
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return ERR_PTR(ret);
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}
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ret = raspberrypi_clock_property(rpi->firmware, data,
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RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
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&max_rate);
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if (ret) {
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dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
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init.name, ret);
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return ERR_PTR(ret);
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}
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if (!min_rate || !max_rate) {
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dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n",
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min_rate, max_rate);
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return ERR_PTR(-EINVAL);
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}
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dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
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min_rate, max_rate);
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data->hw.init = &init;
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ret = devm_clk_hw_register(rpi->dev, &data->hw);
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if (ret)
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return ERR_PTR(ret);
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clk_hw_set_rate_range(&data->hw,
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min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE,
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max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE);
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return &data->hw;
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}
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static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data) {
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.name = "pllb_arm",
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.parent_names = (const char *[]){ "pllb" },
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
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},
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};
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static struct clk_hw *raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
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{
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int ret;
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ret = devm_clk_hw_register(rpi->dev, &raspberrypi_clk_pllb_arm.hw);
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if (ret) {
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dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
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return ERR_PTR(ret);
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}
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ret = devm_clk_hw_register_clkdev(rpi->dev,
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&raspberrypi_clk_pllb_arm.hw,
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NULL, "cpu0");
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if (ret) {
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dev_err(rpi->dev, "Failed to initialize clkdev\n");
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return ERR_PTR(ret);
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}
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return &raspberrypi_clk_pllb_arm.hw;
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}
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static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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@ -341,19 +190,6 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi,
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u32 min_rate, max_rate;
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int ret;
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if (id == RPI_FIRMWARE_ARM_CLK_ID) {
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struct clk_hw *hw;
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hw = raspberrypi_register_pllb(rpi);
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if (IS_ERR(hw)) {
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dev_err(rpi->dev, "Failed to initialize pllb, %ld\n",
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PTR_ERR(hw));
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return hw;
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}
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return raspberrypi_register_pllb_arm(rpi);
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}
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data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return ERR_PTR(-ENOMEM);
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