irqchip: GIC: Add support for irq_[get, set]_irqchip_state()
Add the required hooks for the internal state of an interrupt to be exposed to other subsystems. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Phong Vo <pvo@apm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Tin Huynh <tnhuynh@apm.com> Cc: Y Vo <yvo@apm.com> Cc: Toan Le <toanle@apm.com> Cc: Bjorn Andersson <bjorn@kryo.se> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Arnd Bergmann <arnd@arndb.de> Link: http://lkml.kernel.org/r/1426676484-21812-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Родитель
1b7047edfc
Коммит
567178077c
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@ -151,13 +151,24 @@ static inline unsigned int gic_irq(struct irq_data *d)
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/*
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* Routines to acknowledge, disable and enable interrupts
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*/
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static void gic_mask_irq(struct irq_data *d)
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static void gic_poke_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
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}
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&irq_controller_lock, flags);
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writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
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gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
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if (gic_arch_extn.irq_mask)
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gic_arch_extn.irq_mask(d);
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raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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@ -165,13 +176,12 @@ static void gic_mask_irq(struct irq_data *d)
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static void gic_unmask_irq(struct irq_data *d)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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unsigned long flags;
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raw_spin_lock_irqsave(&irq_controller_lock, flags);
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if (gic_arch_extn.irq_unmask)
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gic_arch_extn.irq_unmask(d);
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writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
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gic_poke_irq(d, GIC_DIST_ENABLE_SET);
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raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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}
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@ -186,6 +196,55 @@ static void gic_eoi_irq(struct irq_data *d)
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writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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}
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static int gic_irq_set_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool val)
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{
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u32 reg;
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
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break;
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case IRQCHIP_STATE_ACTIVE:
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reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
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break;
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case IRQCHIP_STATE_MASKED:
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reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
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break;
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default:
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return -EINVAL;
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}
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gic_poke_irq(d, reg);
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return 0;
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}
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static int gic_irq_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool *val)
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{
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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*val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
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break;
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case IRQCHIP_STATE_ACTIVE:
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*val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
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break;
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case IRQCHIP_STATE_MASKED:
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*val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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void __iomem *base = gic_dist_base(d);
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@ -329,6 +388,8 @@ static struct irq_chip gic_chip = {
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_set_wake = gic_set_wake,
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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};
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void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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