Merge branch '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says: ==================== 10GbE Intel Wired LAN Driver Updates 2018-05-17 This series contains updates to ixgbe, ixgbevf and ice drivers. Cathy Zhou resolves sparse warnings by using the force attribute. Mauro S M Rodrigues fixes a bug where IRQs were not freed if a PCI error recovery system opts to remove the device which causes ixgbe_io_error_detected() to return PCI_ERS_RESULT_DISCONNECT before calling ixgbe_close_suspend() which results in IRQs not freed and crashing when the remove handler calls pci_disable_device(). Resolved this by calling ixgbe_close_suspend() before evaluating the PCI channel state. Pavel Tatashin releases the rtnl_lock during the call to ixgbe_close_suspend() to allow scaling if device_shutdown() is multi-threaded. Emil modifies ixgbe to not validate the MAC address during a reset, unless the MAC was set on the host so that the VF will get a new MAC address every time it reloads. Also updates ixgbevf to set hw->mac.perm_addr in order to retain the custom MAC on a reset. Anirudh updates the ice NVM read/erase/update AQ commands to align with the latest specification. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
56a9a9e737
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@ -1049,7 +1049,9 @@ struct ice_aqc_set_event_mask {
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* NVM Update commands (indirect 0x0703)
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*/
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struct ice_aqc_nvm {
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u8 cmd_flags;
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__le16 offset_low;
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u8 offset_high;
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u8 cmd_flags;
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#define ICE_AQC_NVM_LAST_CMD BIT(0)
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#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
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#define ICE_AQC_NVM_PRESERVATION_S 1
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@ -1058,12 +1060,11 @@ struct ice_aqc_nvm {
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#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
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#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << CSR_AQ_NVM_PRESERVATION_S)
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#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
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u8 module_typeid;
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__le16 length;
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__le16 module_typeid;
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__le16 length;
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#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
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__le32 offset;
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__le32 addr_high;
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__le32 addr_low;
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__le32 addr_high;
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__le32 addr_low;
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};
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/* Get/Set RSS key (indirect 0x0B04/0x0B02) */
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@ -16,7 +16,7 @@
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* Read the NVM using the admin queue commands (0x0701)
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*/
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static enum ice_status
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ice_aq_read_nvm(struct ice_hw *hw, u8 module_typeid, u32 offset, u16 length,
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ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
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void *data, bool last_command, struct ice_sq_cd *cd)
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{
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struct ice_aq_desc desc;
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@ -33,8 +33,9 @@ ice_aq_read_nvm(struct ice_hw *hw, u8 module_typeid, u32 offset, u16 length,
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/* If this is the last command in a series, set the proper flag. */
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if (last_command)
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cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
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cmd->module_typeid = module_typeid;
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cmd->offset = cpu_to_le32(offset);
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cmd->module_typeid = cpu_to_le16(module_typeid);
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cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
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cmd->offset_high = (offset >> 16) & 0xFF;
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cmd->length = cpu_to_le16(length);
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return ice_aq_send_cmd(hw, &desc, data, length, cd);
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@ -1436,7 +1436,8 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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{
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u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
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u32 bucket_hash = 0, hi_dword = 0;
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u32 bucket_hash = 0;
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__be32 hi_dword = 0;
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int i;
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/* Apply masks to input data */
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@ -1475,7 +1476,7 @@ void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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* Limit hash to 13 bits since max bucket count is 8K.
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* Store result at the end of the input stream.
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*/
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input->formatted.bkt_hash = bucket_hash & 0x1FFF;
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input->formatted.bkt_hash = (__force __be16)(bucket_hash & 0x1FFF);
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}
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/**
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@ -1584,7 +1585,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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return IXGBE_ERR_CONFIG;
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}
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switch (input_mask->formatted.flex_bytes & 0xFFFF) {
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switch ((__force u16)input_mask->formatted.flex_bytes & 0xFFFF) {
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case 0x0000:
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/* Mask Flex Bytes */
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fdirm |= IXGBE_FDIRM_FLEX;
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@ -1654,13 +1655,13 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
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/* record vlan (little-endian) and flex_bytes(big-endian) */
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fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
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fdirvlan = IXGBE_STORE_AS_BE16((__force u16)input->formatted.flex_bytes);
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fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
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fdirvlan |= ntohs(input->formatted.vlan_id);
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IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
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/* configure FDIRHASH register */
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fdirhash = input->formatted.bkt_hash;
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fdirhash = (__force u32)input->formatted.bkt_hash;
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fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
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IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
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@ -1698,7 +1699,7 @@ s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
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s32 err;
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/* configure FDIRHASH register */
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fdirhash = input->formatted.bkt_hash;
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fdirhash = (__force u32)input->formatted.bkt_hash;
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fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
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IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
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@ -3626,7 +3626,7 @@ s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
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*/
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for (i = 0; i < dword_len; i++)
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IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
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i, cpu_to_le32(buffer[i]));
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i, (__force u32)cpu_to_le32(buffer[i]));
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/* Setting this bit tells the ARC that a new command is pending. */
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IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
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@ -440,7 +440,7 @@ int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
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case cpu_to_le32(IXGBE_RXDADV_STAT_FCSTAT_FCPRSP):
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dma_unmap_sg(&adapter->pdev->dev, ddp->sgl,
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ddp->sgc, DMA_FROM_DEVICE);
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ddp->err = ddp_err;
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ddp->err = (__force u32)ddp_err;
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ddp->sgl = NULL;
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ddp->sgc = 0;
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/* fall through */
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@ -19,8 +19,9 @@ static void ixgbe_ipsec_set_tx_sa(struct ixgbe_hw *hw, u16 idx,
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int i;
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for (i = 0; i < 4; i++)
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IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(i), cpu_to_be32(key[3 - i]));
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IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, cpu_to_be32(salt));
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IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(i),
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(__force u32)cpu_to_be32(key[3 - i]));
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IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, (__force u32)cpu_to_be32(salt));
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IXGBE_WRITE_FLUSH(hw);
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reg = IXGBE_READ_REG(hw, IXGBE_IPSTXIDX);
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@ -69,7 +70,8 @@ static void ixgbe_ipsec_set_rx_sa(struct ixgbe_hw *hw, u16 idx, __be32 spi,
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int i;
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/* store the SPI (in bigendian) and IPidx */
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI, cpu_to_le32(spi));
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI,
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(__force u32)cpu_to_le32((__force u32)spi));
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPIDX, ip_idx);
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IXGBE_WRITE_FLUSH(hw);
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@ -77,8 +79,9 @@ static void ixgbe_ipsec_set_rx_sa(struct ixgbe_hw *hw, u16 idx, __be32 spi,
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/* store the key, salt, and mode */
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for (i = 0; i < 4; i++)
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(i), cpu_to_be32(key[3 - i]));
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT, cpu_to_be32(salt));
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(i),
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(__force u32)cpu_to_be32(key[3 - i]));
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT, (__force u32)cpu_to_be32(salt));
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXMOD, mode);
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IXGBE_WRITE_FLUSH(hw);
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@ -97,7 +100,8 @@ static void ixgbe_ipsec_set_rx_ip(struct ixgbe_hw *hw, u16 idx, __be32 addr[])
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/* store the ip address */
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for (i = 0; i < 4; i++)
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(i), cpu_to_le32(addr[i]));
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IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(i),
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(__force u32)cpu_to_le32((__force u32)addr[i]));
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IXGBE_WRITE_FLUSH(hw);
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ixgbe_ipsec_set_rx_item(hw, idx, ips_rx_ip_tbl);
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@ -367,7 +371,8 @@ static struct xfrm_state *ixgbe_ipsec_find_rx_state(struct ixgbe_ipsec *ipsec,
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struct xfrm_state *ret = NULL;
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rcu_read_lock();
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hash_for_each_possible_rcu(ipsec->rx_sa_list, rsa, hlist, spi)
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hash_for_each_possible_rcu(ipsec->rx_sa_list, rsa, hlist,
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(__force u32)spi) {
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if (spi == rsa->xs->id.spi &&
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((ip4 && *daddr == rsa->xs->id.daddr.a4) ||
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(!ip4 && !memcmp(daddr, &rsa->xs->id.daddr.a6,
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@ -377,6 +382,7 @@ static struct xfrm_state *ixgbe_ipsec_find_rx_state(struct ixgbe_ipsec *ipsec,
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xfrm_state_hold(ret);
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break;
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}
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}
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rcu_read_unlock();
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return ret;
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}
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@ -569,7 +575,7 @@ static int ixgbe_ipsec_add_sa(struct xfrm_state *xs)
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/* hash the new entry for faster search in Rx path */
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hash_add_rcu(ipsec->rx_sa_list, &ipsec->rx_tbl[sa_idx].hlist,
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rsa.xs->id.spi);
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(__force u64)rsa.xs->id.spi);
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} else {
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struct tx_sa tsa;
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@ -653,7 +659,8 @@ static void ixgbe_ipsec_del_sa(struct xfrm_state *xs)
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if (!ipsec->ip_tbl[ipi].ref_cnt) {
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memset(&ipsec->ip_tbl[ipi], 0,
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sizeof(struct rx_ip_sa));
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ixgbe_ipsec_set_rx_ip(hw, ipi, zerobuf);
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ixgbe_ipsec_set_rx_ip(hw, ipi,
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(__force __be32 *)zerobuf);
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}
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}
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@ -727,8 +727,8 @@ static void ixgbe_dump(struct ixgbe_adapter *adapter)
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ring_desc = "";
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pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
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i,
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le64_to_cpu(u0->a),
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le64_to_cpu(u0->b),
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le64_to_cpu((__force __le64)u0->a),
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le64_to_cpu((__force __le64)u0->b),
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(u64)dma_unmap_addr(tx_buffer, dma),
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dma_unmap_len(tx_buffer, len),
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tx_buffer->next_to_watch,
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@ -839,15 +839,15 @@ rx_ring_summary:
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/* Descriptor Done */
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pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
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i,
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le64_to_cpu(u0->a),
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le64_to_cpu(u0->b),
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le64_to_cpu((__force __le64)u0->a),
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le64_to_cpu((__force __le64)u0->b),
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rx_buffer_info->skb,
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ring_desc);
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} else {
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pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
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i,
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le64_to_cpu(u0->a),
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le64_to_cpu(u0->b),
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le64_to_cpu((__force __le64)u0->a),
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le64_to_cpu((__force __le64)u0->b),
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(u64)rx_buffer_info->dma,
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rx_buffer_info->skb,
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ring_desc);
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@ -6698,8 +6698,15 @@ static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
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rtnl_lock();
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netif_device_detach(netdev);
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if (netif_running(netdev))
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if (netif_running(netdev)) {
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/* Suspend takes a long time, device_shutdown may be
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* parallelized this function, so drop lock for the
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* duration of this call.
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*/
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rtnl_unlock();
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ixgbe_close_suspend(adapter);
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rtnl_lock();
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}
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ixgbe_clear_interrupt_scheme(adapter);
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rtnl_unlock();
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@ -7751,7 +7758,7 @@ static int ixgbe_tso(struct ixgbe_ring *tx_ring,
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/* remove payload length from inner checksum */
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paylen = skb->len - l4_offset;
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csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
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csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
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/* update gso size and bytecount with header size */
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first->gso_segs = skb_shinfo(skb)->gso_segs;
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@ -9104,7 +9111,8 @@ static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
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for (j = 0; field_ptr[j].val; j++) {
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if (field_ptr[j].off == off) {
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field_ptr[j].val(input, mask, val, m);
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field_ptr[j].val(input, mask, (__force u32)val,
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(__force u32)m);
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input->filter.formatted.flow_type |=
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field_ptr[j].type;
|
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found_entry = true;
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|
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@ -9113,8 +9121,10 @@ static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
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}
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if (nexthdr) {
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if (nexthdr->off == cls->knode.sel->keys[i].off &&
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nexthdr->val == cls->knode.sel->keys[i].val &&
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nexthdr->mask == cls->knode.sel->keys[i].mask)
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nexthdr->val ==
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(__force u32)cls->knode.sel->keys[i].val &&
|
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nexthdr->mask ==
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(__force u32)cls->knode.sel->keys[i].mask)
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found_jump_field = true;
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else
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continue;
|
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|
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@ -9218,7 +9228,8 @@ static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
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for (i = 0; nexthdr[i].jump; i++) {
|
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if (nexthdr[i].o != cls->knode.sel->offoff ||
|
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nexthdr[i].s != cls->knode.sel->offshift ||
|
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nexthdr[i].m != cls->knode.sel->offmask)
|
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nexthdr[i].m !=
|
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(__force u32)cls->knode.sel->offmask)
|
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return err;
|
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|
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jump = kzalloc(sizeof(*jump), GFP_KERNEL);
|
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|
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@ -9991,7 +10002,8 @@ static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
|
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}
|
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} else {
|
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for (i = 0; i < adapter->num_rx_queues; i++)
|
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xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog);
|
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(void)xchg(&adapter->rx_ring[i]->xdp_prog,
|
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adapter->xdp_prog);
|
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}
|
||||
|
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if (old_prog)
|
||||
|
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@ -10930,14 +10942,14 @@ skip_bad_vf_detection:
|
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rtnl_lock();
|
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netif_device_detach(netdev);
|
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|
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if (netif_running(netdev))
|
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ixgbe_close_suspend(adapter);
|
||||
|
||||
if (state == pci_channel_io_perm_failure) {
|
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rtnl_unlock();
|
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return PCI_ERS_RESULT_DISCONNECT;
|
||||
}
|
||||
|
||||
if (netif_running(netdev))
|
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ixgbe_close_suspend(adapter);
|
||||
|
||||
if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
|
||||
pci_disable_device(pdev);
|
||||
rtnl_unlock();
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@ static inline int ixgbe_mat_prgm_sip(struct ixgbe_fdir_filter *input,
|
|||
union ixgbe_atr_input *mask,
|
||||
u32 val, u32 m)
|
||||
{
|
||||
input->filter.formatted.src_ip[0] = val;
|
||||
mask->formatted.src_ip[0] = m;
|
||||
input->filter.formatted.src_ip[0] = (__force __be32)val;
|
||||
mask->formatted.src_ip[0] = (__force __be32)m;
|
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return 0;
|
||||
}
|
||||
|
||||
|
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@ -38,8 +38,8 @@ static inline int ixgbe_mat_prgm_dip(struct ixgbe_fdir_filter *input,
|
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union ixgbe_atr_input *mask,
|
||||
u32 val, u32 m)
|
||||
{
|
||||
input->filter.formatted.dst_ip[0] = val;
|
||||
mask->formatted.dst_ip[0] = m;
|
||||
input->filter.formatted.dst_ip[0] = (__force __be32)val;
|
||||
mask->formatted.dst_ip[0] = (__force __be32)m;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -55,10 +55,10 @@ static inline int ixgbe_mat_prgm_ports(struct ixgbe_fdir_filter *input,
|
|||
union ixgbe_atr_input *mask,
|
||||
u32 val, u32 m)
|
||||
{
|
||||
input->filter.formatted.src_port = val & 0xffff;
|
||||
mask->formatted.src_port = m & 0xffff;
|
||||
input->filter.formatted.dst_port = val >> 16;
|
||||
mask->formatted.dst_port = m >> 16;
|
||||
input->filter.formatted.src_port = (__force __be16)(val & 0xffff);
|
||||
mask->formatted.src_port = (__force __be16)(m & 0xffff);
|
||||
input->filter.formatted.dst_port = (__force __be16)(val >> 16);
|
||||
mask->formatted.dst_port = (__force __be16)(m >> 16);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -854,14 +854,11 @@ static int ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf)
|
|||
|
||||
/* reply to reset with ack and vf mac address */
|
||||
msgbuf[0] = IXGBE_VF_RESET;
|
||||
if (!is_zero_ether_addr(vf_mac)) {
|
||||
if (!is_zero_ether_addr(vf_mac) && adapter->vfinfo[vf].pf_set_mac) {
|
||||
msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
|
||||
memcpy(addr, vf_mac, ETH_ALEN);
|
||||
} else {
|
||||
msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
|
||||
dev_warn(&adapter->pdev->dev,
|
||||
"VF %d has no MAC address assigned, you may have to assign one manually\n",
|
||||
vf);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -878,8 +878,9 @@ static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
|
|||
buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
|
||||
|
||||
/* convert offset from words to bytes */
|
||||
buffer.address = cpu_to_be32((offset + current_word) * 2);
|
||||
buffer.length = cpu_to_be16(words_to_read * 2);
|
||||
buffer.address = (__force u32)cpu_to_be32((offset +
|
||||
current_word) * 2);
|
||||
buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
|
||||
buffer.pad2 = 0;
|
||||
buffer.pad3 = 0;
|
||||
|
||||
|
|
@ -1089,9 +1090,9 @@ static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
|
|||
buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
|
||||
|
||||
/* convert offset from words to bytes */
|
||||
buffer.address = cpu_to_be32(offset * 2);
|
||||
buffer.address = (__force u32)cpu_to_be32(offset * 2);
|
||||
/* one word */
|
||||
buffer.length = cpu_to_be16(sizeof(u16));
|
||||
buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
|
||||
|
||||
status = hw->mac.ops.acquire_swfw_sync(hw, mask);
|
||||
if (status)
|
||||
|
|
|
|||
|
|
@ -4164,6 +4164,7 @@ static int ixgbevf_set_mac(struct net_device *netdev, void *p)
|
|||
return -EPERM;
|
||||
|
||||
ether_addr_copy(hw->mac.addr, addr->sa_data);
|
||||
ether_addr_copy(hw->mac.perm_addr, addr->sa_data);
|
||||
ether_addr_copy(netdev->dev_addr, addr->sa_data);
|
||||
|
||||
return 0;
|
||||
|
|
@ -4747,14 +4748,14 @@ static pci_ers_result_t ixgbevf_io_error_detected(struct pci_dev *pdev,
|
|||
rtnl_lock();
|
||||
netif_device_detach(netdev);
|
||||
|
||||
if (netif_running(netdev))
|
||||
ixgbevf_close_suspend(adapter);
|
||||
|
||||
if (state == pci_channel_io_perm_failure) {
|
||||
rtnl_unlock();
|
||||
return PCI_ERS_RESULT_DISCONNECT;
|
||||
}
|
||||
|
||||
if (netif_running(netdev))
|
||||
ixgbevf_close_suspend(adapter);
|
||||
|
||||
if (!test_and_set_bit(__IXGBEVF_DISABLED, &adapter->state))
|
||||
pci_disable_device(pdev);
|
||||
rtnl_unlock();
|
||||
|
|
|
|||
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