PCI: Add sysfs max_link_speed/width, current_link_speed/width, etc
Expose PCIe bridges attributes such as secondary bus number, subordinate bus number, max link speed and link width, current link speed and link width via sysfs in /sys/bus/pci/devices/... This information is available via lspci, but that requires root privilege. Signed-off-by: Wong Vee Khee <vee.khee.wong@ni.com> Signed-off-by: Hui Chun Ong <hui.chun.ong@ni.com> [bhelgaas: changelog, return errors early to unindent usual case, return errors with same style throughout] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Wong Vee Khee
Bjorn Helgaas
Родитель
99b3c58f7b
Коммит
56c1af4606
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@ -154,6 +154,129 @@ static ssize_t resource_show(struct device *dev, struct device_attribute *attr,
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}
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static DEVICE_ATTR_RO(resource);
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static ssize_t max_link_speed_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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const char *speed;
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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switch (linkcap & PCI_EXP_LNKCAP_SLS) {
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case PCI_EXP_LNKCAP_SLS_8_0GB:
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speed = "8 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_5_0GB:
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speed = "5 GT/s";
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break;
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case PCI_EXP_LNKCAP_SLS_2_5GB:
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speed = "2.5 GT/s";
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break;
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default:
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speed = "Unknown speed";
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}
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return sprintf(buf, "%s\n", speed);
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}
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static DEVICE_ATTR_RO(max_link_speed);
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static ssize_t max_link_width_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u32 linkcap;
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int err;
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err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", (linkcap & PCI_EXP_LNKCAP_MLW) >> 4);
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}
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static DEVICE_ATTR_RO(max_link_width);
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static ssize_t current_link_speed_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u16 linkstat;
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int err;
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const char *speed;
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err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
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if (err)
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return -EINVAL;
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switch (linkstat & PCI_EXP_LNKSTA_CLS) {
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case PCI_EXP_LNKSTA_CLS_8_0GB:
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speed = "8 GT/s";
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break;
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case PCI_EXP_LNKSTA_CLS_5_0GB:
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speed = "5 GT/s";
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break;
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case PCI_EXP_LNKSTA_CLS_2_5GB:
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speed = "2.5 GT/s";
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break;
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default:
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speed = "Unknown speed";
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}
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return sprintf(buf, "%s\n", speed);
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}
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static DEVICE_ATTR_RO(current_link_speed);
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static ssize_t current_link_width_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u16 linkstat;
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int err;
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err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n",
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(linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT);
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}
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static DEVICE_ATTR_RO(current_link_width);
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static ssize_t secondary_bus_number_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u8 sec_bus;
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int err;
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err = pci_read_config_byte(pci_dev, PCI_SECONDARY_BUS, &sec_bus);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", sec_bus);
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}
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static DEVICE_ATTR_RO(secondary_bus_number);
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static ssize_t subordinate_bus_number_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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u8 sub_bus;
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int err;
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err = pci_read_config_byte(pci_dev, PCI_SUBORDINATE_BUS, &sub_bus);
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if (err)
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return -EINVAL;
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return sprintf(buf, "%u\n", sub_bus);
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}
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static DEVICE_ATTR_RO(subordinate_bus_number);
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static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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@ -629,12 +752,17 @@ static struct attribute *pci_dev_attrs[] = {
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NULL,
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};
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static const struct attribute_group pci_dev_group = {
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.attrs = pci_dev_attrs,
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static struct attribute *pci_bridge_attrs[] = {
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&dev_attr_subordinate_bus_number.attr,
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&dev_attr_secondary_bus_number.attr,
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NULL,
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};
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const struct attribute_group *pci_dev_groups[] = {
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&pci_dev_group,
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static struct attribute *pcie_dev_attrs[] = {
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&dev_attr_current_link_speed.attr,
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&dev_attr_current_link_width.attr,
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&dev_attr_max_link_width.attr,
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&dev_attr_max_link_speed.attr,
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NULL,
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};
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@ -1557,6 +1685,57 @@ static umode_t pci_dev_hp_attrs_are_visible(struct kobject *kobj,
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return a->mode;
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}
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static umode_t pci_bridge_attrs_are_visible(struct kobject *kobj,
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struct attribute *a, int n)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct pci_dev *pdev = to_pci_dev(dev);
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if (pci_is_bridge(pdev))
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return a->mode;
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return 0;
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}
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static umode_t pcie_dev_attrs_are_visible(struct kobject *kobj,
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struct attribute *a, int n)
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{
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struct device *dev = kobj_to_dev(kobj);
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struct pci_dev *pdev = to_pci_dev(dev);
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if (pci_is_pcie(pdev))
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return a->mode;
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return 0;
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}
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static const struct attribute_group pci_dev_group = {
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.attrs = pci_dev_attrs,
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};
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const struct attribute_group *pci_dev_groups[] = {
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&pci_dev_group,
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NULL,
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};
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static const struct attribute_group pci_bridge_group = {
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.attrs = pci_bridge_attrs,
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};
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const struct attribute_group *pci_bridge_groups[] = {
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&pci_bridge_group,
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NULL,
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};
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static const struct attribute_group pcie_dev_group = {
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.attrs = pcie_dev_attrs,
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};
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const struct attribute_group *pcie_dev_groups[] = {
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&pcie_dev_group,
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NULL,
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};
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static struct attribute_group pci_dev_hp_attr_group = {
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.attrs = pci_dev_hp_attrs,
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.is_visible = pci_dev_hp_attrs_are_visible,
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@ -1592,12 +1771,24 @@ static struct attribute_group pci_dev_attr_group = {
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.is_visible = pci_dev_attrs_are_visible,
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};
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static struct attribute_group pci_bridge_attr_group = {
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.attrs = pci_bridge_attrs,
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.is_visible = pci_bridge_attrs_are_visible,
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};
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static struct attribute_group pcie_dev_attr_group = {
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.attrs = pcie_dev_attrs,
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.is_visible = pcie_dev_attrs_are_visible,
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};
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static const struct attribute_group *pci_dev_attr_groups[] = {
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&pci_dev_attr_group,
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&pci_dev_hp_attr_group,
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#ifdef CONFIG_PCI_IOV
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&sriov_dev_attr_group,
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#endif
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&pci_bridge_attr_group,
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&pcie_dev_attr_group,
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NULL,
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};
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@ -517,6 +517,7 @@
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#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
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#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
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#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
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#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
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#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
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