ARM: tegra: update the cache maintenance order for CPU shutdown
Updating the cache maintenance order before CPU shutdown when doing CPU hotplug. The old order: * clean L1 by flush_cache_all * exit SMP * CPU shutdown Adapt to: * disable L1 data cache by clear C bit * clean L1 by v7_flush_dcache_louis * exit SMP * CPU shutdown For CPU hotplug case, it's no need to do "flush_cache_all". And we should disable L1 data cache before clean L1 data cache. Then leaving the SMP coherency. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -28,8 +28,8 @@ void __ref tegra_cpu_die(unsigned int cpu)
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{
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cpu = cpu_logical_map(cpu);
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/* Flush the L1 data cache. */
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flush_cache_all();
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/* Clean L1 data cache */
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tegra_disable_clean_inv_dcache();
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/* Shut down the current CPU. */
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tegra_hotplug_shutdown();
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@ -33,9 +33,6 @@
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* should never return
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*/
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ENTRY(tegra20_hotplug_shutdown)
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/* Turn off SMP coherency */
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exit_smp r4, r5
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/* Put this CPU down */
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cpu_id r0
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bl tegra20_cpu_shutdown
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@ -32,9 +32,6 @@
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* Should never return.
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*/
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ENTRY(tegra30_hotplug_shutdown)
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/* Turn off SMP coherency */
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exit_smp r4, r5
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/* Powergate this CPU */
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mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
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bl tegra30_cpu_shutdown
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@ -34,7 +34,7 @@
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#include "flowctrl.h"
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#include "sleep.h"
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#ifdef CONFIG_PM_SLEEP
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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/*
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* tegra_disable_clean_inv_dcache
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*
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@ -60,7 +60,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
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ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
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ENDPROC(tegra_disable_clean_inv_dcache)
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#endif
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_sleep_cpu_finish(unsigned long v2p)
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*
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@ -106,6 +106,7 @@ exit_l2_resume:
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#else
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void tegra_resume(void);
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int tegra_sleep_cpu_finish(unsigned long);
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void tegra_disable_clean_inv_dcache(void);
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#ifdef CONFIG_HOTPLUG_CPU
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void tegra20_hotplug_init(void);
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