Watchdog: introduce ARM SBSA watchdog driver
According to Server Base System Architecture (SBSA) specification, the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) is for alerting the system by interrupt, the second one (WS1) is a real hardware reset. More details about the hardware specification of this device: ARM DEN0029B - Server Base System Architecture (SBSA) This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog or a two stages watchdog, it's set up by the module parameter "action". In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. In the two stages mode, when the timeout is reached, the first signal (WS0) will trigger panic. If the system is getting into trouble and cannot be reset by panic or restart properly by the kdump kernel(if supported), then the second stage (as long as the first stage) will be reached, system will be reset by WS1. This function can help administrator to backup the system context info by panic console output or kdump. This driver bases on linux kernel watchdog framework, so it can get timeout from module parameter and FDT at the driver init stage. Signed-off-by: Fu Wei <fu.wei@linaro.org> Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org> Tested-by: Pratyush Anand <panand@redhat.com> Acked-by: Timur Tabi <timur@codeaurora.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Fu Wei
Wim Van Sebroeck
Родитель
2fc94b5f22
Коммит
57d2caaabf
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@ -202,6 +202,26 @@ config ARM_SP805_WATCHDOG
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ARM Primecell SP805 Watchdog timer. This will reboot your system when
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the timeout is reached.
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config ARM_SBSA_WATCHDOG
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tristate "ARM SBSA Generic Watchdog"
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depends on ARM64
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depends on ARM_ARCH_TIMER
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select WATCHDOG_CORE
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help
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ARM SBSA Generic Watchdog has two stage timeouts:
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the first signal (WS0) is for alerting the system by interrupt,
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the second one (WS1) is a real hardware reset.
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More details: ARM DEN0029B - Server Base System Architecture (SBSA)
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This driver can operate ARM SBSA Generic Watchdog as a single stage
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or a two stages watchdog, it depends on the module parameter "action".
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Note: the maximum timeout in the two stages mode is half of that in
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the single stage mode.
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To compile this driver as module, choose M here: The module
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will be called sbsa_gwdt.
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config ASM9260_WATCHDOG
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tristate "Alphascale ASM9260 watchdog"
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depends on MACH_ASM9260
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@ -30,6 +30,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
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# ARM Architecture
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obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
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obj-$(CONFIG_ARM_SBSA_WATCHDOG) += sbsa_gwdt.o
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obj-$(CONFIG_ASM9260_WATCHDOG) += asm9260_wdt.o
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obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
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obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
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@ -0,0 +1,408 @@
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/*
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* SBSA(Server Base System Architecture) Generic Watchdog driver
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*
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* Copyright (c) 2015, Linaro Ltd.
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* Author: Fu Wei <fu.wei@linaro.org>
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* Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
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* Al Stone <al.stone@linaro.org>
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* Timur Tabi <timur@codeaurora.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* ARM SBSA Generic Watchdog has two stage timeouts:
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* the first signal (WS0) is for alerting the system by interrupt,
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* the second one (WS1) is a real hardware reset.
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* More details about the hardware specification of this device:
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* ARM DEN0029B - Server Base System Architecture (SBSA)
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*
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* This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
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* or a two stages watchdog, it's set up by the module parameter "action".
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* In the single stage mode, when the timeout is reached, your system
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* will be reset by WS1. The first signal (WS0) is ignored.
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* In the two stages mode, when the timeout is reached, the first signal (WS0)
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* will trigger panic. If the system is getting into trouble and cannot be reset
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* by panic or restart properly by the kdump kernel(if supported), then the
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* second stage (as long as the first stage) will be reached, system will be
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* reset by WS1. This function can help administrator to backup the system
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* context info by panic console output or kdump.
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*
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* SBSA GWDT:
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* if action is 1 (the two stages mode):
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* |--------WOR-------WS0--------WOR-------WS1
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* |----timeout-----(panic)----timeout-----reset
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*
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* if action is 0 (the single stage mode):
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* |------WOR-----WS0(ignored)-----WOR------WS1
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* |--------------timeout-------------------reset
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*
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* Note: Since this watchdog timer has two stages, and each stage is determined
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* by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
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* stages mode, the timeout is WOR. The maximum timeout in the two stages mode
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* is half of that in the single stage mode.
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*
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*/
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/uaccess.h>
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#include <linux/watchdog.h>
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#include <asm/arch_timer.h>
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#define DRV_NAME "sbsa-gwdt"
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#define WATCHDOG_NAME "SBSA Generic Watchdog"
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/* SBSA Generic Watchdog register definitions */
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/* refresh frame */
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#define SBSA_GWDT_WRR 0x000
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/* control frame */
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#define SBSA_GWDT_WCS 0x000
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#define SBSA_GWDT_WOR 0x008
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#define SBSA_GWDT_WCV 0x010
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/* refresh/control frame */
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#define SBSA_GWDT_W_IIDR 0xfcc
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#define SBSA_GWDT_IDR 0xfd0
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/* Watchdog Control and Status Register */
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#define SBSA_GWDT_WCS_EN BIT(0)
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#define SBSA_GWDT_WCS_WS0 BIT(1)
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#define SBSA_GWDT_WCS_WS1 BIT(2)
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/**
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* struct sbsa_gwdt - Internal representation of the SBSA GWDT
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* @wdd: kernel watchdog_device structure
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* @clk: store the System Counter clock frequency, in Hz.
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* @refresh_base: Virtual address of the watchdog refresh frame
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* @control_base: Virtual address of the watchdog control frame
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*/
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struct sbsa_gwdt {
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struct watchdog_device wdd;
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u32 clk;
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void __iomem *refresh_base;
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void __iomem *control_base;
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};
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#define DEFAULT_TIMEOUT 10 /* seconds */
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static unsigned int timeout;
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module_param(timeout, uint, 0);
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MODULE_PARM_DESC(timeout,
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"Watchdog timeout in seconds. (>=0, default="
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__MODULE_STRING(DEFAULT_TIMEOUT) ")");
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/*
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* action refers to action taken when watchdog gets WS0
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* 0 = skip
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* 1 = panic
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* defaults to skip (0)
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*/
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static int action;
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module_param(action, int, 0);
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MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
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"0 = skip(*) 1 = panic");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, S_IRUGO);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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/*
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* watchdog operation functions
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*/
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static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
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wdd->timeout = timeout;
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if (action)
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writel(gwdt->clk * timeout,
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gwdt->control_base + SBSA_GWDT_WOR);
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else
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/*
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* In the single stage mode, The first signal (WS0) is ignored,
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* the timeout is (WOR * 2), so the WOR should be configured
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* to half value of timeout.
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*/
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writel(gwdt->clk / 2 * timeout,
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gwdt->control_base + SBSA_GWDT_WOR);
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return 0;
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}
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static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
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{
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struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
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u64 timeleft = 0;
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/*
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* In the single stage mode, if WS0 is deasserted
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* (watchdog is in the first stage),
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* timeleft = WOR + (WCV - system counter)
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*/
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if (!action &&
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!(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
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timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);
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timeleft += readq(gwdt->control_base + SBSA_GWDT_WCV) -
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arch_counter_get_cntvct();
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do_div(timeleft, gwdt->clk);
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return timeleft;
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}
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static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
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{
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struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
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/*
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* Writing WRR for an explicit watchdog refresh.
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* You can write anyting (like 0).
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*/
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writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);
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return 0;
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}
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static unsigned int sbsa_gwdt_status(struct watchdog_device *wdd)
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{
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struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
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u32 status = readl(gwdt->control_base + SBSA_GWDT_WCS);
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/* is the watchdog timer running? */
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return (status & SBSA_GWDT_WCS_EN) << WDOG_ACTIVE;
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}
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static int sbsa_gwdt_start(struct watchdog_device *wdd)
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{
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struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
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/* writing WCS will cause an explicit watchdog refresh */
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writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);
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return 0;
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}
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static int sbsa_gwdt_stop(struct watchdog_device *wdd)
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{
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struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
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/* Simply write 0 to WCS to clean WCS_EN bit */
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writel(0, gwdt->control_base + SBSA_GWDT_WCS);
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return 0;
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}
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static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
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{
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panic(WATCHDOG_NAME " timeout");
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return IRQ_HANDLED;
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}
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static struct watchdog_info sbsa_gwdt_info = {
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.identity = WATCHDOG_NAME,
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.options = WDIOF_SETTIMEOUT |
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WDIOF_KEEPALIVEPING |
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WDIOF_MAGICCLOSE |
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WDIOF_CARDRESET,
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};
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static struct watchdog_ops sbsa_gwdt_ops = {
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.owner = THIS_MODULE,
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.start = sbsa_gwdt_start,
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.stop = sbsa_gwdt_stop,
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.status = sbsa_gwdt_status,
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.ping = sbsa_gwdt_keepalive,
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.set_timeout = sbsa_gwdt_set_timeout,
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.get_timeleft = sbsa_gwdt_get_timeleft,
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};
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static int sbsa_gwdt_probe(struct platform_device *pdev)
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{
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void __iomem *rf_base, *cf_base;
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struct device *dev = &pdev->dev;
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struct watchdog_device *wdd;
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struct sbsa_gwdt *gwdt;
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struct resource *res;
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int ret, irq;
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u32 status;
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gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
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if (!gwdt)
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return -ENOMEM;
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platform_set_drvdata(pdev, gwdt);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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cf_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(cf_base))
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return PTR_ERR(cf_base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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rf_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(rf_base))
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return PTR_ERR(rf_base);
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/*
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* Get the frequency of system counter from the cp15 interface of ARM
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* Generic timer. We don't need to check it, because if it returns "0",
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* system would panic in very early stage.
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*/
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gwdt->clk = arch_timer_get_cntfrq();
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gwdt->refresh_base = rf_base;
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gwdt->control_base = cf_base;
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wdd = &gwdt->wdd;
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wdd->parent = dev;
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wdd->info = &sbsa_gwdt_info;
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wdd->ops = &sbsa_gwdt_ops;
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wdd->min_timeout = 1;
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wdd->max_timeout = U32_MAX / gwdt->clk;
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wdd->timeout = DEFAULT_TIMEOUT;
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watchdog_set_drvdata(wdd, gwdt);
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watchdog_set_nowayout(wdd, nowayout);
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status = readl(cf_base + SBSA_GWDT_WCS);
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if (status & SBSA_GWDT_WCS_WS1) {
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dev_warn(dev, "System reset by WDT.\n");
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wdd->bootstatus |= WDIOF_CARDRESET;
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}
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if (action) {
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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action = 0;
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dev_warn(dev, "unable to get ws0 interrupt.\n");
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} else {
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/*
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* In case there is a pending ws0 interrupt, just ping
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* the watchdog before registering the interrupt routine
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*/
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writel(0, rf_base + SBSA_GWDT_WRR);
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if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
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pdev->name, gwdt)) {
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action = 0;
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dev_warn(dev, "unable to request IRQ %d.\n",
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irq);
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}
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}
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if (!action)
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dev_warn(dev, "falling back to single stage mode.\n");
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}
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/*
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* In the single stage mode, The first signal (WS0) is ignored,
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* the timeout is (WOR * 2), so the maximum timeout should be doubled.
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*/
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if (!action)
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wdd->max_timeout *= 2;
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watchdog_init_timeout(wdd, timeout, dev);
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/*
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* Update timeout to WOR.
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* Because of the explicit watchdog refresh mechanism,
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* it's also a ping, if watchdog is enabled.
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*/
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sbsa_gwdt_set_timeout(wdd, wdd->timeout);
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ret = watchdog_register_device(wdd);
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if (ret)
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return ret;
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dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
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wdd->timeout, gwdt->clk, action,
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status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");
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return 0;
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}
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static void sbsa_gwdt_shutdown(struct platform_device *pdev)
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{
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struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
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sbsa_gwdt_stop(&gwdt->wdd);
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}
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static int sbsa_gwdt_remove(struct platform_device *pdev)
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{
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struct sbsa_gwdt *gwdt = platform_get_drvdata(pdev);
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watchdog_unregister_device(&gwdt->wdd);
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return 0;
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}
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/* Disable watchdog if it is active during suspend */
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static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
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{
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struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
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if (watchdog_active(&gwdt->wdd))
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sbsa_gwdt_stop(&gwdt->wdd);
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return 0;
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}
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/* Enable watchdog if necessary */
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static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
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{
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struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
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if (watchdog_active(&gwdt->wdd))
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sbsa_gwdt_start(&gwdt->wdd);
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return 0;
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}
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static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
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};
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static const struct of_device_id sbsa_gwdt_of_match[] = {
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{ .compatible = "arm,sbsa-gwdt", },
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{},
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};
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MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
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static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
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{ .name = DRV_NAME, },
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||||
{},
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};
|
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MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
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||||
|
||||
static struct platform_driver sbsa_gwdt_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.pm = &sbsa_gwdt_pm_ops,
|
||||
.of_match_table = sbsa_gwdt_of_match,
|
||||
},
|
||||
.probe = sbsa_gwdt_probe,
|
||||
.remove = sbsa_gwdt_remove,
|
||||
.shutdown = sbsa_gwdt_shutdown,
|
||||
.id_table = sbsa_gwdt_pdev_match,
|
||||
};
|
||||
|
||||
module_platform_driver(sbsa_gwdt_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
|
||||
MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
|
||||
MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
|
||||
MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
|
||||
MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
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