dmfe: stop using net_device.{base_addr, irq} and convert to __iomem.
This is a pure PCI driver, no ISA here. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Acked-by: Grant Grundler <grundler@parisc-linux.org>
This commit is contained in:
Francois Romieu
Родитель
aae9bc302d
Коммит
5820e97a29
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@ -150,6 +150,12 @@
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#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
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#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
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#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
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#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
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#define dr32(reg) ioread32(ioaddr + (reg))
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#define dr16(reg) ioread16(ioaddr + (reg))
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#define dr8(reg) ioread8(ioaddr + (reg))
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#define DMFE_DBUG(dbug_now, msg, value) \
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do { \
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if (dmfe_debug || (dbug_now)) \
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@ -178,14 +184,6 @@
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#define SROM_V41_CODE 0x14
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#define SROM_CLK_WRITE(data, ioaddr) \
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outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
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udelay(5); \
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outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
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udelay(5); \
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outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
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udelay(5);
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#define __CHK_IO_SIZE(pci_id, dev_rev) \
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(( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
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DM9102A_IO_SIZE: DM9102_IO_SIZE)
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@ -213,11 +211,11 @@ struct rx_desc {
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struct dmfe_board_info {
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u32 chip_id; /* Chip vendor/Device ID */
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u8 chip_revision; /* Chip revision */
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struct DEVICE *next_dev; /* next device */
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struct net_device *next_dev; /* next device */
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struct pci_dev *pdev; /* PCI device */
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spinlock_t lock;
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long ioaddr; /* I/O base address */
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void __iomem *ioaddr; /* I/O base address */
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u32 cr0_data;
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u32 cr5_data;
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u32 cr6_data;
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@ -320,20 +318,20 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
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static int dmfe_stop(struct DEVICE *);
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static void dmfe_set_filter_mode(struct DEVICE *);
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static const struct ethtool_ops netdev_ethtool_ops;
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static u16 read_srom_word(long ,int);
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static u16 read_srom_word(void __iomem *, int);
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static irqreturn_t dmfe_interrupt(int , void *);
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#ifdef CONFIG_NET_POLL_CONTROLLER
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static void poll_dmfe (struct net_device *dev);
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#endif
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static void dmfe_descriptor_init(struct net_device *, unsigned long);
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static void dmfe_descriptor_init(struct net_device *);
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static void allocate_rx_buffer(struct net_device *);
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static void update_cr6(u32, unsigned long);
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static void update_cr6(u32, void __iomem *);
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static void send_filter_frame(struct DEVICE *);
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static void dm9132_id_table(struct DEVICE *);
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static u16 phy_read(unsigned long, u8, u8, u32);
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static void phy_write(unsigned long, u8, u8, u16, u32);
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static void phy_write_1bit(unsigned long, u32);
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static u16 phy_read_1bit(unsigned long);
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static u16 phy_read(void __iomem *, u8, u8, u32);
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static void phy_write(void __iomem *, u8, u8, u16, u32);
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static void phy_write_1bit(void __iomem *, u32);
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static u16 phy_read_1bit(void __iomem *);
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static u8 dmfe_sense_speed(struct dmfe_board_info *);
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static void dmfe_process_mode(struct dmfe_board_info *);
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static void dmfe_timer(unsigned long);
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@ -462,14 +460,16 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
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db->buf_pool_dma_start = db->buf_pool_dma_ptr;
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db->chip_id = ent->driver_data;
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db->ioaddr = pci_resource_start(pdev, 0);
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/* IO type range. */
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db->ioaddr = pci_iomap(pdev, 0, 0);
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if (!db->ioaddr)
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goto err_out_free_buf;
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db->chip_revision = pdev->revision;
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db->wol_mode = 0;
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db->pdev = pdev;
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dev->base_addr = db->ioaddr;
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dev->irq = pdev->irq;
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pci_set_drvdata(pdev, dev);
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dev->netdev_ops = &netdev_ops;
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dev->ethtool_ops = &netdev_ethtool_ops;
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@ -484,9 +484,10 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
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db->chip_type = 0;
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/* read 64 word srom data */
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for (i = 0; i < 64; i++)
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for (i = 0; i < 64; i++) {
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((__le16 *) db->srom)[i] =
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cpu_to_le16(read_srom_word(db->ioaddr, i));
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}
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/* Set Node address */
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for (i = 0; i < 6; i++)
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@ -494,16 +495,18 @@ static int __devinit dmfe_init_one (struct pci_dev *pdev,
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err = register_netdev (dev);
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if (err)
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goto err_out_free_buf;
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goto err_out_unmap;
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dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
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ent->driver_data >> 16,
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pci_name(pdev), dev->dev_addr, dev->irq);
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pci_name(pdev), dev->dev_addr, pdev->irq);
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pci_set_master(pdev);
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return 0;
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err_out_unmap:
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pci_iounmap(pdev, db->ioaddr);
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err_out_free_buf:
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pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
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db->buf_pool_ptr, db->buf_pool_dma_ptr);
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@ -532,7 +535,7 @@ static void __devexit dmfe_remove_one (struct pci_dev *pdev)
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if (dev) {
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unregister_netdev(dev);
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pci_iounmap(db->pdev, db->ioaddr);
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pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
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DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
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db->desc_pool_dma_ptr);
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@ -555,13 +558,13 @@ static void __devexit dmfe_remove_one (struct pci_dev *pdev)
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static int dmfe_open(struct DEVICE *dev)
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{
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int ret;
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struct dmfe_board_info *db = netdev_priv(dev);
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const int irq = db->pdev->irq;
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int ret;
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DMFE_DBUG(0, "dmfe_open", 0);
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ret = request_irq(dev->irq, dmfe_interrupt,
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IRQF_SHARED, dev->name, dev);
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ret = request_irq(irq, dmfe_interrupt, IRQF_SHARED, dev->name, dev);
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if (ret)
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return ret;
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@ -615,14 +618,14 @@ static int dmfe_open(struct DEVICE *dev)
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static void dmfe_init_dm910x(struct DEVICE *dev)
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{
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struct dmfe_board_info *db = netdev_priv(dev);
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unsigned long ioaddr = db->ioaddr;
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void __iomem *ioaddr = db->ioaddr;
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DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
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/* Reset DM910x MAC controller */
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outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
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dw32(DCR0, DM910X_RESET); /* RESET MAC */
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udelay(100);
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outl(db->cr0_data, ioaddr + DCR0);
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dw32(DCR0, db->cr0_data);
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udelay(5);
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/* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
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@ -633,12 +636,12 @@ static void dmfe_init_dm910x(struct DEVICE *dev)
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db->media_mode = dmfe_media_mode;
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/* RESET Phyxcer Chip by GPR port bit 7 */
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outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
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dw32(DCR12, 0x180); /* Let bit 7 output port */
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if (db->chip_id == PCI_DM9009_ID) {
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outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
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dw32(DCR12, 0x80); /* Issue RESET signal */
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mdelay(300); /* Delay 300 ms */
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}
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outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
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dw32(DCR12, 0x0); /* Clear RESET signal */
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/* Process Phyxcer Media Mode */
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if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
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@ -649,7 +652,7 @@ static void dmfe_init_dm910x(struct DEVICE *dev)
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db->op_mode = db->media_mode; /* Force Mode */
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/* Initialize Transmit/Receive decriptor and CR3/4 */
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dmfe_descriptor_init(dev, ioaddr);
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dmfe_descriptor_init(dev);
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/* Init CR6 to program DM910x operation */
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update_cr6(db->cr6_data, ioaddr);
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@ -662,10 +665,10 @@ static void dmfe_init_dm910x(struct DEVICE *dev)
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/* Init CR7, interrupt active bit */
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db->cr7_data = CR7_DEFAULT;
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outl(db->cr7_data, ioaddr + DCR7);
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dw32(DCR7, db->cr7_data);
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/* Init CR15, Tx jabber and Rx watchdog timer */
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outl(db->cr15_data, ioaddr + DCR15);
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dw32(DCR15, db->cr15_data);
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/* Enable DM910X Tx/Rx function */
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db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
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@ -682,6 +685,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
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struct DEVICE *dev)
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{
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struct dmfe_board_info *db = netdev_priv(dev);
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void __iomem *ioaddr = db->ioaddr;
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struct tx_desc *txptr;
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unsigned long flags;
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@ -707,7 +711,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
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}
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/* Disable NIC interrupt */
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outl(0, dev->base_addr + DCR7);
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dw32(DCR7, 0);
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/* transmit this packet */
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txptr = db->tx_insert_ptr;
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@ -721,11 +725,11 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
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if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
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txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
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db->tx_packet_cnt++; /* Ready to send */
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outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
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dw32(DCR1, 0x1); /* Issue Tx polling */
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dev->trans_start = jiffies; /* saved time stamp */
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} else {
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db->tx_queue_cnt++; /* queue TX packet */
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outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
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dw32(DCR1, 0x1); /* Issue Tx polling */
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}
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/* Tx resource check */
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@ -734,7 +738,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
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/* Restore CR7 to enable interrupt */
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spin_unlock_irqrestore(&db->lock, flags);
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outl(db->cr7_data, dev->base_addr + DCR7);
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dw32(DCR7, db->cr7_data);
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/* free this SKB */
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dev_kfree_skb(skb);
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@ -751,7 +755,7 @@ static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
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static int dmfe_stop(struct DEVICE *dev)
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{
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struct dmfe_board_info *db = netdev_priv(dev);
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unsigned long ioaddr = dev->base_addr;
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void __iomem *ioaddr = db->ioaddr;
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DMFE_DBUG(0, "dmfe_stop", 0);
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@ -762,12 +766,12 @@ static int dmfe_stop(struct DEVICE *dev)
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del_timer_sync(&db->timer);
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/* Reset & stop DM910X board */
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outl(DM910X_RESET, ioaddr + DCR0);
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dw32(DCR0, DM910X_RESET);
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udelay(5);
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phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
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phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
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/* free interrupt */
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free_irq(dev->irq, dev);
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free_irq(db->pdev->irq, dev);
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/* free allocated rx buffer */
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dmfe_free_rxbuffer(db);
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@ -794,7 +798,7 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
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{
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struct DEVICE *dev = dev_id;
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struct dmfe_board_info *db = netdev_priv(dev);
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unsigned long ioaddr = dev->base_addr;
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void __iomem *ioaddr = db->ioaddr;
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unsigned long flags;
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DMFE_DBUG(0, "dmfe_interrupt()", 0);
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@ -802,15 +806,15 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
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spin_lock_irqsave(&db->lock, flags);
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/* Got DM910X status */
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db->cr5_data = inl(ioaddr + DCR5);
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outl(db->cr5_data, ioaddr + DCR5);
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db->cr5_data = dr32(DCR5);
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dw32(DCR5, db->cr5_data);
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if ( !(db->cr5_data & 0xc1) ) {
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spin_unlock_irqrestore(&db->lock, flags);
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return IRQ_HANDLED;
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}
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/* Disable all interrupt in CR7 to solve the interrupt edge problem */
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outl(0, ioaddr + DCR7);
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dw32(DCR7, 0);
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/* Check system status */
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if (db->cr5_data & 0x2000) {
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@ -838,11 +842,11 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
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if (db->dm910x_chk_mode & 0x2) {
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db->dm910x_chk_mode = 0x4;
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db->cr6_data |= 0x100;
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update_cr6(db->cr6_data, db->ioaddr);
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update_cr6(db->cr6_data, ioaddr);
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}
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/* Restore CR7 to enable interrupt mask */
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outl(db->cr7_data, ioaddr + DCR7);
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dw32(DCR7, db->cr7_data);
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spin_unlock_irqrestore(&db->lock, flags);
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return IRQ_HANDLED;
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@ -858,11 +862,14 @@ static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
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static void poll_dmfe (struct net_device *dev)
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{
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struct dmfe_board_info *db = netdev_priv(dev);
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const int irq = db->pdev->irq;
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/* disable_irq here is not very nice, but with the lockless
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interrupt handler we have no other choice. */
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disable_irq(dev->irq);
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dmfe_interrupt (dev->irq, dev);
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enable_irq(dev->irq);
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disable_irq(irq);
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dmfe_interrupt (irq, dev);
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enable_irq(irq);
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}
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#endif
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@ -873,7 +880,7 @@ static void poll_dmfe (struct net_device *dev)
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static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
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{
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struct tx_desc *txptr;
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unsigned long ioaddr = dev->base_addr;
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void __iomem *ioaddr = db->ioaddr;
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u32 tdes0;
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txptr = db->tx_remove_ptr;
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@ -897,7 +904,7 @@ static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
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db->tx_fifo_underrun++;
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if ( !(db->cr6_data & CR6_SFT) ) {
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db->cr6_data = db->cr6_data | CR6_SFT;
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update_cr6(db->cr6_data, db->ioaddr);
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update_cr6(db->cr6_data, ioaddr);
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}
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}
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if (tdes0 & 0x0100)
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@ -924,7 +931,7 @@ static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
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txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
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db->tx_packet_cnt++; /* Ready to send */
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db->tx_queue_cnt--;
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outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
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dw32(DCR1, 0x1); /* Issue Tx polling */
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dev->trans_start = jiffies; /* saved time stamp */
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}
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@ -1087,12 +1094,7 @@ static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
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strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
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strlcpy(info->version, DRV_VERSION, sizeof(info->version));
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if (np->pdev)
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strlcpy(info->bus_info, pci_name(np->pdev),
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sizeof(info->bus_info));
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else
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sprintf(info->bus_info, "EISA 0x%lx %d",
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dev->base_addr, dev->irq);
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strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
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}
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static int dmfe_ethtool_set_wol(struct net_device *dev,
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@ -1132,10 +1134,11 @@ static const struct ethtool_ops netdev_ethtool_ops = {
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static void dmfe_timer(unsigned long data)
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{
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struct net_device *dev = (struct net_device *)data;
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struct dmfe_board_info *db = netdev_priv(dev);
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void __iomem *ioaddr = db->ioaddr;
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u32 tmp_cr8;
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unsigned char tmp_cr12;
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struct DEVICE *dev = (struct DEVICE *) data;
|
||||
struct dmfe_board_info *db = netdev_priv(dev);
|
||||
unsigned long flags;
|
||||
|
||||
int link_ok, link_ok_phy;
|
||||
|
|
@ -1148,11 +1151,10 @@ static void dmfe_timer(unsigned long data)
|
|||
db->first_in_callback = 1;
|
||||
if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
|
||||
db->cr6_data &= ~0x40000;
|
||||
update_cr6(db->cr6_data, db->ioaddr);
|
||||
phy_write(db->ioaddr,
|
||||
db->phy_addr, 0, 0x1000, db->chip_id);
|
||||
update_cr6(db->cr6_data, ioaddr);
|
||||
phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
|
||||
db->cr6_data |= 0x40000;
|
||||
update_cr6(db->cr6_data, db->ioaddr);
|
||||
update_cr6(db->cr6_data, ioaddr);
|
||||
db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
|
||||
add_timer(&db->timer);
|
||||
spin_unlock_irqrestore(&db->lock, flags);
|
||||
|
|
@ -1167,7 +1169,7 @@ static void dmfe_timer(unsigned long data)
|
|||
db->dm910x_chk_mode = 0x4;
|
||||
|
||||
/* Dynamic reset DM910X : system error or transmit time-out */
|
||||
tmp_cr8 = inl(db->ioaddr + DCR8);
|
||||
tmp_cr8 = dr32(DCR8);
|
||||
if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
|
||||
db->reset_cr8++;
|
||||
db->wait_reset = 1;
|
||||
|
|
@ -1177,7 +1179,7 @@ static void dmfe_timer(unsigned long data)
|
|||
/* TX polling kick monitor */
|
||||
if ( db->tx_packet_cnt &&
|
||||
time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
|
||||
outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
|
||||
dw32(DCR1, 0x1); /* Tx polling again */
|
||||
|
||||
/* TX Timeout */
|
||||
if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
|
||||
|
|
@ -1200,9 +1202,9 @@ static void dmfe_timer(unsigned long data)
|
|||
|
||||
/* Link status check, Dynamic media type change */
|
||||
if (db->chip_id == PCI_DM9132_ID)
|
||||
tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
|
||||
tmp_cr12 = dr8(DCR9 + 3); /* DM9132 */
|
||||
else
|
||||
tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
|
||||
tmp_cr12 = dr8(DCR12); /* DM9102/DM9102A */
|
||||
|
||||
if ( ((db->chip_id == PCI_DM9102_ID) &&
|
||||
(db->chip_revision == 0x30)) ||
|
||||
|
|
@ -1251,7 +1253,7 @@ static void dmfe_timer(unsigned long data)
|
|||
/* 10/100M link failed, used 1M Home-Net */
|
||||
db->cr6_data|=0x00040000; /* bit18=1, MII */
|
||||
db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
|
||||
update_cr6(db->cr6_data, db->ioaddr);
|
||||
update_cr6(db->cr6_data, ioaddr);
|
||||
}
|
||||
} else if (!netif_carrier_ok(dev)) {
|
||||
|
||||
|
|
@ -1288,17 +1290,18 @@ static void dmfe_timer(unsigned long data)
|
|||
* Re-initialize DM910X board
|
||||
*/
|
||||
|
||||
static void dmfe_dynamic_reset(struct DEVICE *dev)
|
||||
static void dmfe_dynamic_reset(struct net_device *dev)
|
||||
{
|
||||
struct dmfe_board_info *db = netdev_priv(dev);
|
||||
void __iomem *ioaddr = db->ioaddr;
|
||||
|
||||
DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
|
||||
|
||||
/* Sopt MAC controller */
|
||||
db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
|
||||
update_cr6(db->cr6_data, dev->base_addr);
|
||||
outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
|
||||
outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
|
||||
update_cr6(db->cr6_data, ioaddr);
|
||||
dw32(DCR7, 0); /* Disable Interrupt */
|
||||
dw32(DCR5, dr32(DCR5));
|
||||
|
||||
/* Disable upper layer interface */
|
||||
netif_stop_queue(dev);
|
||||
|
|
@ -1364,9 +1367,10 @@ static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
|
|||
* Using Chain structure, and allocate Tx/Rx buffer
|
||||
*/
|
||||
|
||||
static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr)
|
||||
static void dmfe_descriptor_init(struct net_device *dev)
|
||||
{
|
||||
struct dmfe_board_info *db = netdev_priv(dev);
|
||||
void __iomem *ioaddr = db->ioaddr;
|
||||
struct tx_desc *tmp_tx;
|
||||
struct rx_desc *tmp_rx;
|
||||
unsigned char *tmp_buf;
|
||||
|
|
@ -1379,7 +1383,7 @@ static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr)
|
|||
/* tx descriptor start pointer */
|
||||
db->tx_insert_ptr = db->first_tx_desc;
|
||||
db->tx_remove_ptr = db->first_tx_desc;
|
||||
outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
|
||||
dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
|
||||
|
||||
/* rx descriptor start pointer */
|
||||
db->first_rx_desc = (void *)db->first_tx_desc +
|
||||
|
|
@ -1389,7 +1393,7 @@ static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr)
|
|||
sizeof(struct tx_desc) * TX_DESC_CNT;
|
||||
db->rx_insert_ptr = db->first_rx_desc;
|
||||
db->rx_ready_ptr = db->first_rx_desc;
|
||||
outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
|
||||
dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
|
||||
|
||||
/* Init Transmit chain */
|
||||
tmp_buf = db->buf_pool_start;
|
||||
|
|
@ -1431,14 +1435,14 @@ static void dmfe_descriptor_init(struct net_device *dev, unsigned long ioaddr)
|
|||
* Firstly stop DM910X , then written value and start
|
||||
*/
|
||||
|
||||
static void update_cr6(u32 cr6_data, unsigned long ioaddr)
|
||||
static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
|
||||
{
|
||||
u32 cr6_tmp;
|
||||
|
||||
cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
|
||||
outl(cr6_tmp, ioaddr + DCR6);
|
||||
dw32(DCR6, cr6_tmp);
|
||||
udelay(5);
|
||||
outl(cr6_data, ioaddr + DCR6);
|
||||
dw32(DCR6, cr6_data);
|
||||
udelay(5);
|
||||
}
|
||||
|
||||
|
|
@ -1448,24 +1452,19 @@ static void update_cr6(u32 cr6_data, unsigned long ioaddr)
|
|||
* This setup frame initialize DM910X address filter mode
|
||||
*/
|
||||
|
||||
static void dm9132_id_table(struct DEVICE *dev)
|
||||
static void dm9132_id_table(struct net_device *dev)
|
||||
{
|
||||
struct dmfe_board_info *db = netdev_priv(dev);
|
||||
void __iomem *ioaddr = db->ioaddr + 0xc0;
|
||||
u16 *addrptr = (u16 *)dev->dev_addr;
|
||||
struct netdev_hw_addr *ha;
|
||||
u16 * addrptr;
|
||||
unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
|
||||
u32 hash_val;
|
||||
u16 i, hash_table[4];
|
||||
|
||||
DMFE_DBUG(0, "dm9132_id_table()", 0);
|
||||
|
||||
/* Node address */
|
||||
addrptr = (u16 *) dev->dev_addr;
|
||||
outw(addrptr[0], ioaddr);
|
||||
ioaddr += 4;
|
||||
outw(addrptr[1], ioaddr);
|
||||
ioaddr += 4;
|
||||
outw(addrptr[2], ioaddr);
|
||||
ioaddr += 4;
|
||||
for (i = 0; i < 3; i++) {
|
||||
dw16(0, addrptr[i]);
|
||||
ioaddr += 4;
|
||||
}
|
||||
|
||||
/* Clear Hash Table */
|
||||
memset(hash_table, 0, sizeof(hash_table));
|
||||
|
|
@ -1475,13 +1474,14 @@ static void dm9132_id_table(struct DEVICE *dev)
|
|||
|
||||
/* the multicast address in Hash Table : 64 bits */
|
||||
netdev_for_each_mc_addr(ha, dev) {
|
||||
hash_val = cal_CRC((char *) ha->addr, 6, 0) & 0x3f;
|
||||
u32 hash_val = cal_CRC((char *)ha->addr, 6, 0) & 0x3f;
|
||||
|
||||
hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
|
||||
}
|
||||
|
||||
/* Write the hash table to MAC MD table */
|
||||
for (i = 0; i < 4; i++, ioaddr += 4)
|
||||
outw(hash_table[i], ioaddr);
|
||||
dw16(0, hash_table[i]);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1490,7 +1490,7 @@ static void dm9132_id_table(struct DEVICE *dev)
|
|||
* This setup frame initialize DM910X address filter mode
|
||||
*/
|
||||
|
||||
static void send_filter_frame(struct DEVICE *dev)
|
||||
static void send_filter_frame(struct net_device *dev)
|
||||
{
|
||||
struct dmfe_board_info *db = netdev_priv(dev);
|
||||
struct netdev_hw_addr *ha;
|
||||
|
|
@ -1535,12 +1535,14 @@ static void send_filter_frame(struct DEVICE *dev)
|
|||
|
||||
/* Resource Check and Send the setup packet */
|
||||
if (!db->tx_packet_cnt) {
|
||||
void __iomem *ioaddr = db->ioaddr;
|
||||
|
||||
/* Resource Empty */
|
||||
db->tx_packet_cnt++;
|
||||
txptr->tdes0 = cpu_to_le32(0x80000000);
|
||||
update_cr6(db->cr6_data | 0x2000, dev->base_addr);
|
||||
outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
|
||||
update_cr6(db->cr6_data, dev->base_addr);
|
||||
update_cr6(db->cr6_data | 0x2000, ioaddr);
|
||||
dw32(DCR1, 0x1); /* Issue Tx polling */
|
||||
update_cr6(db->cr6_data, ioaddr);
|
||||
dev->trans_start = jiffies;
|
||||
} else
|
||||
db->tx_queue_cnt++; /* Put in TX queue */
|
||||
|
|
@ -1575,43 +1577,55 @@ static void allocate_rx_buffer(struct net_device *dev)
|
|||
db->rx_insert_ptr = rxptr;
|
||||
}
|
||||
|
||||
static void srom_clk_write(void __iomem *ioaddr, u32 data)
|
||||
{
|
||||
static const u32 cmd[] = {
|
||||
CR9_SROM_READ | CR9_SRCS,
|
||||
CR9_SROM_READ | CR9_SRCS | CR9_SRCLK,
|
||||
CR9_SROM_READ | CR9_SRCS
|
||||
};
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cmd); i++) {
|
||||
dw32(DCR9, data | cmd[i]);
|
||||
udelay(5);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Read one word data from the serial ROM
|
||||
*/
|
||||
|
||||
static u16 read_srom_word(long ioaddr, int offset)
|
||||
static u16 read_srom_word(void __iomem *ioaddr, int offset)
|
||||
{
|
||||
u16 srom_data;
|
||||
int i;
|
||||
u16 srom_data = 0;
|
||||
long cr9_ioaddr = ioaddr + DCR9;
|
||||
|
||||
outl(CR9_SROM_READ, cr9_ioaddr);
|
||||
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
|
||||
dw32(DCR9, CR9_SROM_READ);
|
||||
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
|
||||
|
||||
/* Send the Read Command 110b */
|
||||
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
|
||||
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
|
||||
SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
|
||||
srom_clk_write(ioaddr, SROM_DATA_1);
|
||||
srom_clk_write(ioaddr, SROM_DATA_1);
|
||||
srom_clk_write(ioaddr, SROM_DATA_0);
|
||||
|
||||
/* Send the offset */
|
||||
for (i = 5; i >= 0; i--) {
|
||||
srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
|
||||
SROM_CLK_WRITE(srom_data, cr9_ioaddr);
|
||||
srom_clk_write(ioaddr, srom_data);
|
||||
}
|
||||
|
||||
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
|
||||
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
|
||||
|
||||
for (i = 16; i > 0; i--) {
|
||||
outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
|
||||
dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
|
||||
udelay(5);
|
||||
srom_data = (srom_data << 1) |
|
||||
((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
|
||||
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
|
||||
((dr32(DCR9) & CR9_CRDOUT) ? 1 : 0);
|
||||
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
|
||||
udelay(5);
|
||||
}
|
||||
|
||||
outl(CR9_SROM_READ, cr9_ioaddr);
|
||||
dw32(DCR9, CR9_SROM_READ);
|
||||
return srom_data;
|
||||
}
|
||||
|
||||
|
|
@ -1620,13 +1634,14 @@ static u16 read_srom_word(long ioaddr, int offset)
|
|||
* Auto sense the media mode
|
||||
*/
|
||||
|
||||
static u8 dmfe_sense_speed(struct dmfe_board_info * db)
|
||||
static u8 dmfe_sense_speed(struct dmfe_board_info *db)
|
||||
{
|
||||
void __iomem *ioaddr = db->ioaddr;
|
||||
u8 ErrFlag = 0;
|
||||
u16 phy_mode;
|
||||
|
||||
/* CR6 bit18=0, select 10/100M */
|
||||
update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
|
||||
update_cr6(db->cr6_data & ~0x40000, ioaddr);
|
||||
|
||||
phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
|
||||
phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
|
||||
|
|
@ -1665,11 +1680,12 @@ static u8 dmfe_sense_speed(struct dmfe_board_info * db)
|
|||
|
||||
static void dmfe_set_phyxcer(struct dmfe_board_info *db)
|
||||
{
|
||||
void __iomem *ioaddr = db->ioaddr;
|
||||
u16 phy_reg;
|
||||
|
||||
/* Select 10/100M phyxcer */
|
||||
db->cr6_data &= ~0x40000;
|
||||
update_cr6(db->cr6_data, db->ioaddr);
|
||||
update_cr6(db->cr6_data, ioaddr);
|
||||
|
||||
/* DM9009 Chip: Phyxcer reg18 bit12=0 */
|
||||
if (db->chip_id == PCI_DM9009_ID) {
|
||||
|
|
@ -1765,18 +1781,15 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
|
|||
* Write a word to Phy register
|
||||
*/
|
||||
|
||||
static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
|
||||
static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
|
||||
u16 phy_data, u32 chip_id)
|
||||
{
|
||||
u16 i;
|
||||
unsigned long ioaddr;
|
||||
|
||||
if (chip_id == PCI_DM9132_ID) {
|
||||
ioaddr = iobase + 0x80 + offset * 4;
|
||||
outw(phy_data, ioaddr);
|
||||
dw16(0x80 + offset * 4, phy_data);
|
||||
} else {
|
||||
/* DM9102/DM9102A Chip */
|
||||
ioaddr = iobase + DCR9;
|
||||
|
||||
/* Send 33 synchronization clock to Phy controller */
|
||||
for (i = 0; i < 35; i++)
|
||||
|
|
@ -1816,19 +1829,16 @@ static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
|
|||
* Read a word data from phy register
|
||||
*/
|
||||
|
||||
static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
|
||||
static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
|
||||
{
|
||||
int i;
|
||||
u16 phy_data;
|
||||
unsigned long ioaddr;
|
||||
|
||||
if (chip_id == PCI_DM9132_ID) {
|
||||
/* DM9132 Chip */
|
||||
ioaddr = iobase + 0x80 + offset * 4;
|
||||
phy_data = inw(ioaddr);
|
||||
phy_data = dr16(0x80 + offset * 4);
|
||||
} else {
|
||||
/* DM9102/DM9102A Chip */
|
||||
ioaddr = iobase + DCR9;
|
||||
|
||||
/* Send 33 synchronization clock to Phy controller */
|
||||
for (i = 0; i < 35; i++)
|
||||
|
|
@ -1870,13 +1880,13 @@ static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
|
|||
* Write one bit data to Phy Controller
|
||||
*/
|
||||
|
||||
static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
|
||||
static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
|
||||
{
|
||||
outl(phy_data, ioaddr); /* MII Clock Low */
|
||||
dw32(DCR9, phy_data); /* MII Clock Low */
|
||||
udelay(1);
|
||||
outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
|
||||
dw32(DCR9, phy_data | MDCLKH); /* MII Clock High */
|
||||
udelay(1);
|
||||
outl(phy_data, ioaddr); /* MII Clock Low */
|
||||
dw32(DCR9, phy_data); /* MII Clock Low */
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
|
|
@ -1885,14 +1895,14 @@ static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
|
|||
* Read one bit phy data from PHY controller
|
||||
*/
|
||||
|
||||
static u16 phy_read_1bit(unsigned long ioaddr)
|
||||
static u16 phy_read_1bit(void __iomem *ioaddr)
|
||||
{
|
||||
u16 phy_data;
|
||||
|
||||
outl(0x50000, ioaddr);
|
||||
dw32(DCR9, 0x50000);
|
||||
udelay(1);
|
||||
phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
|
||||
outl(0x40000, ioaddr);
|
||||
phy_data = (dr32(DCR9) >> 19) & 0x1;
|
||||
dw32(DCR9, 0x40000);
|
||||
udelay(1);
|
||||
|
||||
return phy_data;
|
||||
|
|
@ -1978,7 +1988,7 @@ static void dmfe_parse_srom(struct dmfe_board_info * db)
|
|||
|
||||
/* Check DM9801 or DM9802 present or not */
|
||||
db->HPNA_present = 0;
|
||||
update_cr6(db->cr6_data|0x40000, db->ioaddr);
|
||||
update_cr6(db->cr6_data | 0x40000, db->ioaddr);
|
||||
tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
|
||||
if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
|
||||
/* DM9801 or DM9802 present */
|
||||
|
|
@ -2095,6 +2105,7 @@ static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
|
|||
{
|
||||
struct net_device *dev = pci_get_drvdata(pci_dev);
|
||||
struct dmfe_board_info *db = netdev_priv(dev);
|
||||
void __iomem *ioaddr = db->ioaddr;
|
||||
u32 tmp;
|
||||
|
||||
/* Disable upper layer interface */
|
||||
|
|
@ -2102,11 +2113,11 @@ static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
|
|||
|
||||
/* Disable Tx/Rx */
|
||||
db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
|
||||
update_cr6(db->cr6_data, dev->base_addr);
|
||||
update_cr6(db->cr6_data, ioaddr);
|
||||
|
||||
/* Disable Interrupt */
|
||||
outl(0, dev->base_addr + DCR7);
|
||||
outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
|
||||
dw32(DCR7, 0);
|
||||
dw32(DCR5, dr32(DCR5));
|
||||
|
||||
/* Fre RX buffers */
|
||||
dmfe_free_rxbuffer(db);
|
||||
|
|
|
|||
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