kvm: vmx: Introduce lapic_mode enumeration
The local APIC can be in one of three modes: disabled, xAPIC or x2APIC. (A fourth mode, "invalid," is included for completeness.) Using the new enumeration can make some of the APIC mode logic easier to read. In kvm_set_apic_base, for instance, it is clear that one cannot transition directly from x2APIC mode to xAPIC mode or directly from APIC disabled to x2APIC mode. Signed-off-by: Jim Mattson <jmattson@google.com> Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com> [Check invalid bits even if msr_info->host_initiated. Reported by Wanpeng Li. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -16,6 +16,13 @@
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#define APIC_BUS_CYCLE_NS 1
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#define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS)
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enum lapic_mode {
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LAPIC_MODE_DISABLED = 0,
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LAPIC_MODE_INVALID = X2APIC_ENABLE,
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LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
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LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
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};
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struct kvm_timer {
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struct hrtimer timer;
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s64 period; /* unit: ns */
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@ -89,6 +96,7 @@ u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
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int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
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int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
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int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
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enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
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u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
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@ -220,4 +228,10 @@ void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
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void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
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bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
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void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
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static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
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{
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return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
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}
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#endif
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@ -318,23 +318,27 @@ u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
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}
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EXPORT_SYMBOL_GPL(kvm_get_apic_base);
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enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
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{
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return kvm_apic_mode(kvm_get_apic_base(vcpu));
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}
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EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
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int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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u64 old_state = vcpu->arch.apic_base &
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(MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
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u64 new_state = msr_info->data &
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(MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
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enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
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enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
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u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
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(guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
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if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
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if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
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return 1;
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if (!msr_info->host_initiated &&
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((new_state == MSR_IA32_APICBASE_ENABLE &&
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old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
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(new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
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old_state == 0)))
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if (!msr_info->host_initiated) {
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if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
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return 1;
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if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
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return 1;
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}
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kvm_lapic_set_base(vcpu, msr_info->data);
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return 0;
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