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i.MX arm64 device tree changes for 6.4: 

- New board device trees: Apalis quadmax, DH electronics i.MX8M Plus
   DHCOM and PDK3, Data Modul i.MX8M Plus eDM SBC, Colibri Aster and
   Iris, etc.
 - Add FlexSPI, BBNSM and TPM PWM devices for i.MX93 SoC.
 - A series of imx8mq-librem5 udpates which includes minor fixes,
   magnetometer, CSI/camera support, and powersaving improvements.
 - Add Cadence USB3 support for i.MX8QXP.
 - Add FlexCAN support for i.MX8QXP and i.MX8QM.
 - Add UART DMA support for i.MX8MQ.
 - Add GPT devices for i.MX8MP.
 - Add VPU decoder and encoder support for i.MX8QM.
 - Add display pipeline and PCIe EP support for i.MX8M family SoCs.
 - A series from Peng Fan updating various i.MX8M device trees to pinctrl
   nodes match DT schema.
 - A series from Philippe Schenker improving colibri-imx8x device trees
   in various aspects.
 - Other random device tree updates.
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Merge tag 'imx-dt64-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree changes for 6.4:

- New board device trees: Apalis quadmax, DH electronics i.MX8M Plus
  DHCOM and PDK3, Data Modul i.MX8M Plus eDM SBC, Colibri Aster and
  Iris, etc.
- Add FlexSPI, BBNSM and TPM PWM devices for i.MX93 SoC.
- A series of imx8mq-librem5 udpates which includes minor fixes,
  magnetometer, CSI/camera support, and powersaving improvements.
- Add Cadence USB3 support for i.MX8QXP.
- Add FlexCAN support for i.MX8QXP and i.MX8QM.
- Add UART DMA support for i.MX8MQ.
- Add GPT devices for i.MX8MP.
- Add VPU decoder and encoder support for i.MX8QM.
- Add display pipeline and PCIe EP support for i.MX8M family SoCs.
- A series from Peng Fan updating various i.MX8M device trees to pinctrl
  nodes match DT schema.
- A series from Philippe Schenker improving colibri-imx8x device trees
  in various aspects.
- Other random device tree updates.

* tag 'imx-dt64-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (87 commits)
  arm64: dts: imx8mp: Add support for Data Modul i.MX8M Plus eDM SBC
  arm64: dts: imx8mp: Add display pipeline components
  arm64: dts: imx8mn: Add display pipeline components
  arm64: dts: imx8mm: Add display pipeline components
  arm64: dts: freescale: imx8qxp-mek: enable cadence usb3
  arm64: dts: imx8qxp: add cadence usb3 support
  arm64: dts: imx8mq-librem5: add missing #clock-cells
  arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschema
  arm64: dts: imx8mn-bsh-smm: update pinctrl to match dtschema
  arm64: dts: imx8mm-emcon: update pinctrl to match dtschema
  arm64: dts: imx8mq-librem5: update pinctrl to match dtschema
  arm64: dts: imx8mm-ddr4-evk: update gpmi pinctrl to match dtschema
  arm64: dts: imx8mn-evk: update i2c pinctrl to match dtschema
  arm64: dts: imx8mp: Add GPT blocks
  arm64: dts: imx8-apalis-v1.1: drop ci-disable-lpm
  arm64: dts: imx8dxl: drop clocks from scu clock controller
  arm64: dts: imx8mp: verdin-yavia: drop disable-over-current
  arm64: dts: imx8mq: tqma8mq-mba8mx: drop disable-over-current
  arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK3
  arm64: dts: colibri-imx8x: Add iris v2 carrier board
  ...

Link: https://lore.kernel.org/r/20230408101928.280271-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-14 17:28:58 +02:00
Родитель 0efb9fa003 562d222f23
Коммит 58982e1d3c
66 изменённых файлов: 5914 добавлений и 747 удалений
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10
arch/arm64/boot/dts/freescale/Makefile
Просмотреть файл

@ -89,8 +89,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
@ -122,9 +124,17 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb

2
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
Просмотреть файл

@ -131,7 +131,7 @@
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
its: gic-its@6020000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */

2
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
Просмотреть файл

@ -123,7 +123,7 @@
#size-cells = <2>;
ranges;
its: gic-its@6020000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x6020000 0 0x20000>;

2
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
Просмотреть файл

@ -60,7 +60,7 @@
interrupt-controller;
interrupts = <1 9 0x4>;
its: gic-its@6020000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x6020000 0 0x20000>;

2
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
Просмотреть файл

@ -395,7 +395,7 @@
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its: gic-its@6020000 {
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x6020000 0 0x20000>;

144
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi Normal file
Просмотреть файл

@ -0,0 +1,144 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/ {
aliases {
rtc0 = &rtc_i2c;
rtc1 = &rtc;
};
reg_usb_host_vbus: regulator-usb-host-vbus {
regulator-name = "VCC USBH2(ABCD) / USBH(3|4)";
};
};
&adc0 {
status = "okay";
};
&adc1 {
status = "okay";
};
/* TODO: Audio Mixer */
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
/* TODO: Display Controller */
/* TODO: DPU */
/* Apalis ETH1 */
&fec1 {
status = "okay";
};
/* Apalis CAN1 */
&flexcan1 {
status = "okay";
};
/* Apalis CAN2 */
&flexcan2 {
status = "okay";
};
/* TODO: GPU */
/* Apalis I2C1 */
&i2c2 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
status = "okay";
};
};
/* Apalis I2C3 (CAM) */
&i2c3 {
status = "okay";
};
/* Apalis SPI1 */
&lpspi0 {
status = "okay";
};
/* Apalis SPI2 */
&lpspi2 {
status = "okay";
};
/* Apalis UART3 */
&lpuart0 {
status = "okay";
};
/* Apalis UART1 */
&lpuart1 {
status = "okay";
};
/* Apalis UART4 */
&lpuart2 {
status = "okay";
};
/* Apalis UART2 */
&lpuart3 {
status = "okay";
};
/* Apalis PWM3, MXM3 pin 6 */
&lsio_pwm0 {
status = "okay";
};
/* Apalis PWM4, MXM3 pin 8 */
&lsio_pwm1 {
status = "okay";
};
/* Apalis PWM1, MXM3 pin 2 */
&lsio_pwm2 {
status = "okay";
};
/* Apalis PWM2, MXM3 pin 4 */
&lsio_pwm3 {
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* TODO: Apalis BKL1_PWM */
/* TODO: Apalis DAP1 */
/* TODO: Apalis Analogue Audio */
/* TODO: Apalis SATA1 */
/* TODO: Apalis SPDIF1 */
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
/* Apalis USBO1 */
&usbotg1 {
status = "okay";
};
/* TODO: Apalis USBH4 SuperSpeed */
/* Apalis MMC1 */
&usdhc2 {
status = "okay";
};
/* Apalis SD1 */
&usdhc3 {
status = "okay";
};

220
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi Normal file
Просмотреть файл

@ -0,0 +1,220 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include <dt-bindings/leds/common.h>
/ {
aliases {
rtc0 = &rtc_i2c;
rtc1 = &rtc;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_ixora>;
/* LED_4_GREEN / MXM3_188 */
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>;
};
/* LED_4_RED / MXM3_178 */
led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>;
};
/* LED_5_GREEN / MXM3_152 */
led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
};
/* LED_5_RED / MXM3_156 */
led-4 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
};
};
reg_usb_host_vbus: regulator-usb-host-vbus {
regulator-name = "VCC_USBH(2|4)";
};
};
&adc0 {
status = "okay";
};
&adc1 {
status = "okay";
};
/* TODO: Audio Mixer */
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
/* TODO: Display Controller */
/* TODO: DPU */
/* Apalis ETH1 */
&fec1 {
status = "okay";
};
/* Apalis CAN1 */
&flexcan1 {
status = "okay";
};
/* Apalis CAN2 */
&flexcan2 {
status = "okay";
};
/* TODO: GPU */
/* Apalis I2C1 */
&i2c2 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
status = "okay";
};
};
/* Apalis I2C3 (CAM) */
&i2c3 {
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>,
<&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
<&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
<&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
<&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
<&pinctrl_sim0_gpios>, <&pinctrl_uart24_forceoff>,
<&pinctrl_usdhc1_gpios>;
pinctrl_leds_ixora: ledsixoragrp {
fsl,pins = <IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x06000061>, /* LED_4_GREEN */
<IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x06000061>, /* LED_4_RED */
<IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x06000061>, /* LED_5_GREEN */
<IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x06000061>; /* LED_5_RED */
};
pinctrl_uart24_forceoff: uart24forceoffgrp {
fsl,pins = <IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x00000021>;
};
};
/* Apalis SPI1 */
&lpspi0 {
status = "okay";
};
/* Apalis SPI2 */
&lpspi2 {
status = "okay";
};
/* Apalis UART3 */
&lpuart0 {
status = "okay";
};
/* Apalis UART1 */
&lpuart1 {
status = "okay";
};
/* Apalis UART4 */
&lpuart2 {
status = "okay";
};
/* Apalis UART2 */
&lpuart3 {
status = "okay";
};
&lsio_gpio5 {
gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03",
"gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07",
"gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11",
"gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15",
"gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19",
"LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23",
"gpio5-24", "UART24-FORCEOFF", "gpio5-26",
"LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",
"gpio5-31";
ngpios = <32>;
};
/* Apalis PWM3, MXM3 pin 6 */
&lsio_pwm0 {
status = "okay";
};
/* Apalis PWM4, MXM3 pin 8 */
&lsio_pwm1 {
status = "okay";
};
/* Apalis PWM1, MXM3 pin 2 */
&lsio_pwm2 {
status = "okay";
};
/* Apalis PWM2, MXM3 pin 4 */
&lsio_pwm3 {
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* TODO: Apalis BKL1_PWM */
/* TODO: Apalis DAP1 */
/* TODO: Apalis Analogue Audio */
/* TODO: Apalis SATA1 */
/* TODO: Apalis SPDIF1 */
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
/* Apalis USBO1 */
&usbotg1 {
status = "okay";
};
/* TODO: Apalis USBH4 SuperSpeed */
/* Apalis MMC1 */
&usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>;
pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>;
pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>;
pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>;
bus-width = <4>;
status = "okay";
};

270
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi Normal file
Просмотреть файл

@ -0,0 +1,270 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include <dt-bindings/leds/common.h>
/ {
aliases {
rtc0 = &rtc_i2c;
rtc1 = &rtc;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_ixora>;
/* LED_4_GREEN / MXM3_188 */
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>;
};
/* LED_4_RED / MXM3_178 */
led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>;
};
/* LED_5_GREEN / MXM3_152 */
led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
};
/* LED_5_RED / MXM3_156 */
led-4 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
};
};
reg_3v3_vmmc: regulator-3v3-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
/* MMC1_PWR_CTRL */
gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3v3_vmmc";
};
reg_can1_supply: regulator-can1-supply {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can1_power>;
gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-name = "can1_supply";
};
reg_can2_supply: regulator-can2-supply {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sata1_act>;
gpio = <&lsio_gpio2 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-name = "can2_supply";
};
reg_usb_host_vbus: regulator-usb-host-vbus {
regulator-name = "VCC_USBH(2|4)";
};
};
&adc0 {
status = "okay";
};
&adc1 {
status = "okay";
};
/* TODO: Audio Mixer */
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
/* TODO: Display Controller */
/* TODO: DPU */
/* Apalis ETH1 */
&fec1 {
status = "okay";
};
/* Apalis CAN1 */
&flexcan1 {
xceiver-supply = <&reg_can1_supply>;
status = "okay";
};
/* Apalis CAN2 */
&flexcan2 {
xceiver-supply = <&reg_can2_supply>;
status = "okay";
};
/* TODO: GPU */
/* Apalis I2C1 */
&i2c2 {
status = "okay";
eeprom: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
status = "okay";
};
};
/* Apalis I2C3 (CAM) */
&i2c3 {
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>,
<&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
<&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
<&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
<&pinctrl_qspi1a_gpios>, <&pinctrl_sim0_gpios>,
<&pinctrl_uart24_forceoff>, <&pinctrl_usdhc1_gpios>;
/* PMIC MMC1 power-switch */
pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148, PMIC */
};
/* FlexCAN PMIC */
pinctrl_enable_can1_power: enablecan1powergrp {
fsl,pins = <IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>; /* MXM3_158, PMIC */
};
pinctrl_leds_ixora: ledsixoragrp {
fsl,pins = <IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x06000061>, /* LED_4_GREEN */
<IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x06000061>, /* LED_4_RED */
<IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x06000061>, /* LED_5_GREEN */
<IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x06000061>; /* LED_5_RED */
};
pinctrl_uart24_forceoff: uart24forceoffgrp {
fsl,pins = <IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x00000021>;
};
};
/* Apalis SPI1 */
&lpspi0 {
status = "okay";
};
/* Apalis SPI2 */
&lpspi2 {
status = "okay";
};
/* Apalis UART3 */
&lpuart0 {
status = "okay";
};
/* Apalis UART1 */
&lpuart1 {
status = "okay";
};
/* Apalis UART4 */
&lpuart2 {
status = "okay";
};
/* Apalis UART2 */
&lpuart3 {
status = "okay";
};
&lsio_gpio5 {
gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03",
"gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07",
"gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11",
"gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15",
"gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19",
"LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23",
"gpio5-24", "UART24-FORCEOFF", "gpio5-26",
"LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30",
"gpio5-31";
ngpios = <32>;
};
/* Apalis PWM3, MXM3 pin 6 */
&lsio_pwm0 {
status = "okay";
};
/* Apalis PWM4, MXM3 pin 8 */
&lsio_pwm1 {
status = "okay";
};
/* Apalis PWM1, MXM3 pin 2 */
&lsio_pwm2 {
status = "okay";
};
/* Apalis PWM2, MXM3 pin 4 */
&lsio_pwm3 {
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* TODO: Apalis BKL1_PWM */
/* TODO: Apalis DAP1 */
/* TODO: Apalis Analogue Audio */
/* TODO: Apalis SATA1 */
/* TODO: Apalis SPDIF1 */
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
/* Apalis USBO1 */
&usbotg1 {
status = "okay";
};
/* TODO: Apalis USBH4 SuperSpeed */
/* Apalis MMC1 */
&usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>;
pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>;
pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>;
pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>;
bus-width = <4>;
cap-power-off-card;
/delete-property/ no-1-8-v;
vmmc-supply = <&reg_3v3_vmmc>;
status = "okay";
};

1484
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi Normal file
Просмотреть файл

Разница между файлами не показана из-за своего большого размера Загрузить разницу

69
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
Просмотреть файл

@ -138,6 +138,53 @@ conn_subsys: bus@5b000000 {
status = "disabled";
};
usbotg3: usb@5b110000 {
compatible = "fsl,imx8qm-usb3";
reg = <0x5b110000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
<&usb3_lpcg IMX_LPCG_CLK_0>,
<&usb3_lpcg IMX_LPCG_CLK_7>,
<&usb3_lpcg IMX_LPCG_CLK_4>,
<&usb3_lpcg IMX_LPCG_CLK_5>;
clock-names = "lpm", "bus", "aclk", "ipg", "core";
assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
assigned-clock-rates = <250000000>;
power-domains = <&pd IMX_SC_R_USB_2>;
status = "disabled";
usbotg3_cdns3: usb@5b120000 {
compatible = "cdns,usb3";
reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
<0x5b140000 0x10000>, /* memory area for DEVICE registers */
<0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
reg-names = "xhci", "dev", "otg";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host", "peripheral", "otg", "wakeup";
phys = <&usb3_phy>;
phy-names = "cdns3,usb3-phy";
status = "disabled";
};
};
usb3_phy: usb-phy@5b160000 {
compatible = "nxp,salvo-phy";
reg = <0x5b160000 0x40000>;
clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
clock-names = "salvo_phy_clk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
#phy-cells = <0>;
status = "disabled";
};
/* LPCG clocks */
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
@ -234,4 +281,26 @@ conn_subsys: bus@5b000000 {
clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
};
usb3_lpcg: clock-controller@5b280000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b280000 0x10000>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
<&conn_ipg_clk>,
<&conn_ipg_clk>,
<&conn_ipg_clk>,
<&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
clock-output-names = "usb3_app_clk",
"usb3_lpm_clk",
"usb3_ipg_clk",
"usb3_core_pclk",
"usb3_phy_clk",
"usb3_aclk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
};
};

76
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
Просмотреть файл

@ -31,7 +31,7 @@ dma_subsys: bus@5a000000 {
<&spi0_lpcg 1>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <20000000>;
assigned-clock-rates = <60000000>;
power-domains = <&pd IMX_SC_R_SPI_0>;
status = "disabled";
};
@ -270,6 +270,7 @@ dma_subsys: bus@5a000000 {
adc0: adc@5a880000 {
compatible = "nxp,imx8qxp-adc";
#io-channel-cells = <1>;
reg = <0x5a880000 0x10000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@ -284,6 +285,7 @@ dma_subsys: bus@5a000000 {
adc1: adc@5a890000 {
compatible = "nxp,imx8qxp-adc";
#io-channel-cells = <1>;
reg = <0x5a890000 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@ -296,6 +298,65 @@ dma_subsys: bus@5a000000 {
status = "disabled";
};
flexcan1: can@5a8d0000 {
compatible = "fsl,imx8qm-flexcan";
reg = <0x5a8d0000 0x10000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&can0_lpcg 1>,
<&can0_lpcg 0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
power-domains = <&pd IMX_SC_R_CAN_0>;
/* SLSlice[4] */
fsl,clk-source = /bits/ 8 <0>;
fsl,scu-index = /bits/ 8 <0>;
status = "disabled";
};
flexcan2: can@5a8e0000 {
compatible = "fsl,imx8qm-flexcan";
reg = <0x5a8e0000 0x10000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* CAN0 clock and PD is shared among all CAN instances as
* CAN1 shares CAN0's clock and to enable CAN0's clock it
* has to be powered on.
*/
clocks = <&can0_lpcg 1>,
<&can0_lpcg 0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
power-domains = <&pd IMX_SC_R_CAN_1>;
/* SLSlice[4] */
fsl,clk-source = /bits/ 8 <0>;
fsl,scu-index = /bits/ 8 <1>;
status = "disabled";
};
flexcan3: can@5a8f0000 {
compatible = "fsl,imx8qm-flexcan";
reg = <0x5a8f0000 0x10000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* CAN0 clock and PD is shared among all CAN instances as
* CAN2 shares CAN0's clock and to enable CAN0's clock it
* has to be powered on.
*/
clocks = <&can0_lpcg 1>,
<&can0_lpcg 0>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <40000000>;
power-domains = <&pd IMX_SC_R_CAN_2>;
/* SLSlice[4] */
fsl,clk-source = /bits/ 8 <0>;
fsl,scu-index = /bits/ 8 <2>;
status = "disabled";
};
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
@ -367,4 +428,17 @@ dma_subsys: bus@5a000000 {
"adc1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ADC_1>;
};
can0_lpcg: clock-controller@5acd0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5acd0000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>, <&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
clock-output-names = "can0_lpcg_pe_clk",
"can0_lpcg_ipg_clk",
"can0_lpcg_chi_clk";
power-domains = <&pd IMX_SC_R_CAN_0>;
};
};

48
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
Просмотреть файл

@ -28,6 +28,54 @@ lsio_subsys: bus@5d000000 {
clock-output-names = "lsio_bus_clk";
};
lsio_pwm0: pwm@5d000000 {
compatible = "fsl,imx27-pwm";
reg = <0x5d000000 0x10000>;
clock-names = "ipg", "per";
clocks = <&pwm0_lpcg 4>,
<&pwm0_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
status = "disabled";
};
lsio_pwm1: pwm@5d010000 {
compatible = "fsl,imx27-pwm";
reg = <0x5d010000 0x10000>;
clock-names = "ipg", "per";
clocks = <&pwm1_lpcg 4>,
<&pwm1_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
status = "disabled";
};
lsio_pwm2: pwm@5d020000 {
compatible = "fsl,imx27-pwm";
reg = <0x5d020000 0x10000>;
clock-names = "ipg", "per";
clocks = <&pwm2_lpcg 4>,
<&pwm2_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
status = "disabled";
};
lsio_pwm3: pwm@5d030000 {
compatible = "fsl,imx27-pwm";
reg = <0x5d030000 0x10000>;
clock-names = "ipg", "per";
clocks = <&pwm3_lpcg 4>,
<&pwm3_lpcg 1>;
assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
#pwm-cells = <2>;
status = "disabled";
};
lsio_gpio0: gpio@5d080000 {
reg = <0x5d080000 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
Просмотреть файл

@ -276,7 +276,7 @@
};
&thermal_zones {
pmic-thermal0 {
pmic-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;

4
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
Просмотреть файл

@ -130,8 +130,6 @@
clk: clock-controller {
compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
#clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
scu_gpio: gpio {
@ -188,7 +186,7 @@
};
thermal_zones: thermal-zones {
cpu-thermal0 {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;

2
arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
Просмотреть файл

@ -28,7 +28,7 @@
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096

4
arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
Просмотреть файл

@ -124,7 +124,7 @@
>;
};
pinctrl_ecspi1_cs: ecspi1-cs {
pinctrl_ecspi1_cs: ecspi1cs-grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
@ -215,7 +215,7 @@
>;
};
pinctrl_pmic: pmic-irq {
pinctrl_pmic: pmicirq-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41
>;

13
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
Просмотреть файл

@ -168,6 +168,12 @@
"", "ECSPI1_SS0";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
};
/* PCIe */
&pcie0 {
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
@ -333,6 +339,13 @@
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
pinctrl_leds: leds1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16

4
arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
Просмотреть файл

@ -264,7 +264,7 @@
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
@ -280,7 +280,7 @@
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6

79
arch/arm64/boot/dts/freescale/imx8mm.dtsi
Просмотреть файл

@ -1119,6 +1119,61 @@
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
lcdif: lcdif@32e00000 {
compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
reg = <0x32e00000 0x10000>;
clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
<&clk IMX8MM_CLK_DISP_AXI>,
<&clk IMX8MM_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
<&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
mipi_dsi: dsi@32e10000 {
compatible = "fsl,imx8mm-mipi-dsim";
reg = <0x32e10000 0x400>;
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <266000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
};
csi: csi@32e20000 {
compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
reg = <0x32e20000 0x1000>;
@ -1315,6 +1370,30 @@
status = "disabled";
};
pcie0_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mm-pcie-ep";
reg = <0x33800000 0x400000>,
<0x18000000 0x8000000>;
reg-names = "dbi", "addr_space";
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
fsl,max-link-speed = <2>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
status = "disabled";
};
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;

6
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
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@ -341,7 +341,7 @@
>;
};
pinctrl_pmic: pmicirq {
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
>;
@ -381,7 +381,7 @@
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
@ -392,7 +392,7 @@
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6

2
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts
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@ -26,7 +26,7 @@
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096

4
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts
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@ -136,7 +136,7 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
@ -152,7 +152,7 @@
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6

4
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
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@ -389,7 +389,7 @@
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
@ -403,7 +403,7 @@
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3

55
arch/arm64/boot/dts/freescale/imx8mn.dtsi
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@ -1057,6 +1057,61 @@
#size-cells = <1>;
ranges;
lcdif: lcdif@32e00000 {
compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
reg = <0x32e00000 0x10000>;
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif>;
};
};
};
mipi_dsi: dsi@32e10000 {
compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
reg = <0x32e10000 0x400>;
clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
<&clk IMX8MN_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_CLK_24M>;
assigned-clock-rates = <266000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dsim>;
};
};
};
};
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;

977
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts Normal file
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@ -0,0 +1,977 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include <dt-bindings/net/qca-ar803x.h>
#include "imx8mp.dtsi"
/ {
model = "Data Modul i.MX8M Plus eDM SBC";
compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart3;
};
memory@40000000 {
device_type = "memory";
/* There are 1/2/4 GiB options, adjusted by bootloader. */
reg = <0x0 0x40000000 0 0x40000000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_backlight>;
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
default-brightness-level = <7>;
enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
pwms = <&pwm1 0 5000000 0>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
clk_xtal25: clock-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
panel: panel {
/* Compatible string is filled in by panel board DT Overlay. */
backlight = <&backlight>;
power-supply = <&reg_panel_vcc>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
reg_panel_vcc: regulator-panel-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_vcc_reg>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "PANEL_VCC";
/* GPIO flags are ignored, enable-active-high applies. */
gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3_SD";
/* GPIO flags are ignored, enable-active-high applies. */
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */
enable-active-high;
off-on-delay-us = <12000>;
startup-delay-us = <100>;
vin-supply = <&buck4>;
};
watchdog { /* TPS3813 */
compatible = "linux,wdt-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog_gpio>;
always-running;
gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
hw_algo = "level";
/* Reset triggers in 2..3 seconds */
hw_margin_ms = <1500>;
/* Disabled by default */
status = "disabled";
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 { /* W25Q128JVEI */
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>; /* Up to 133 MHz */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&ecspi2 { /* Feature connector SPI */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
/* Disabled by default, unless feature board plugged in. */
status = "disabled";
};
&ecspi3 { /* Display connector SPI */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
&eqos { /* First ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-handle = <&phy_eqos>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8031 PHY */
phy_eqos: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/*
* Dedicated ENET_WOL# signal is unused, the PHY
* can wake the SoC up via INT signal as well.
*/
interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
qca,keep-pll-enabled;
vddio-supply = <&vddio_eqos>;
vddio_eqos: vddio-regulator {
regulator-name = "VDDIO_EQOS";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh_eqos: vddh-regulator {
regulator-name = "VDDH_EQOS";
};
};
};
};
&fec { /* Second ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-handle = <&phy_fec>;
phy-mode = "rgmii-id";
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8031 PHY */
phy_fec: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/*
* Dedicated ENET_WOL# signal is unused, the PHY
* can wake the SoC up via INT signal as well.
*/
interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
qca,keep-pll-enabled;
vddio-supply = <&vddio_fec>;
vddio_fec: vddio-regulator {
regulator-name = "VDDIO_FEC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh_fec: vddh-regulator {
regulator-name = "VDDH_FEC";
};
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&gpio1 {
gpio-line-names =
"", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",
"", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",
"GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",
"", "", "", "ENET_RST#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "ENET2_INT#", "", "", "", "", "",
"WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",
"", "", "", "",
"", "", "", "SD2_RESET#", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
"CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",
"", "", "EEPROM_WP_1V8#", "", "", "", "", "",
"MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",
"", "M2_W_DISABLE1_1V8#",
"M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",
"", "", "", "";
};
&gpio4 {
gpio-line-names =
"DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",
"", "DIS_USB_DN1", "DIS_USB_DN2", "",
"", "", "", "", "", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "", "", "", "WDOG_EN", "", "",
"", "SPI1_CS#", "", "",
"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
"", "", "", "",
"", "SPI3_CS#", "", "", "", "", "", "";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
usb-hub@2c {
compatible = "microchip,usb2514bi";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_hub>;
individual-port-switching;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
self-powered;
};
eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
rtc: rtc@68 {
compatible = "st,m41t62";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
};
pcieclk: clk@6a {
compatible = "renesas,9fgv0241";
reg = <0x6a>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
/*
* i.MX 8M Plus Data Sheet for Consumer Products
* 3.1.4 Operating ranges
* MIMX8ML8CVNKZAB
*/
regulators {
buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <3125>;
regulator-always-on;
regulator-boot-on;
};
buck2: BUCK2 { /* VDD_ARM */
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <3125>;
regulator-always-on;
regulator-boot-on;
};
buck4: BUCK4 { /* VDD_3V3 */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
buck5: BUCK5 { /* VDD_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
buck6: BUCK6 { /* NVCC_DRAM_1V1 */
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
ldo1: LDO1 { /* NVCC_SNVS_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3: LDO3 { /* VDDA_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4: LDO4 { /* PMIC_LDO4 */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5: LDO5 { /* NVCC_SD2 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&i2c5 { /* HDMI EDID bus */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
pinctrl-1 = <&pinctrl_i2c5_gpio>;
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_pwm>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
/* SD slot */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
vmmc-supply = <&buck4>;
vqmmc-supply = <&buck5>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&uart1 { /* RS485 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "disabled"; /* Optional */
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&uart3 { /* A53 Debug */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
fsl,over-current-active-low;
status = "okay";
};
&usb_dwc3_0 { /* Lower plug direct */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
dr_mode = "host";
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 { /* Upper plug via HUB */
dr_mode = "host";
status = "okay";
};
&wdog1 {
status = "okay";
};
/* IOMUXC node should be at the end of DT to improve readability. */
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
<&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
<&pinctrl_panel_expansion>;
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
>;
};
pinctrl_ecspi2: ecspi2-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
>;
};
pinctrl_ecspi3: ecspi3-grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44
MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44
MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44
MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40
>;
};
pinctrl_eqos: eqos-grp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
/* ENET_RST# */
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6
/* ENET_INT# */
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090
>;
};
pinctrl_fec: fec-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
/* ENET2_RST# */
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6
/* ENET2_INT# */
MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
>;
};
pinctrl_flexcan1: flexcan1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_hog_feature: hog-feature-grp {
fsl,pins = <
/* GPIO5_IO03 */
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006
/* GPIO5_IO04 */
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006
/* CAN_INT# */
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090
>;
};
pinctrl_hog_panel: hog-panel-grp {
fsl,pins = <
/* GRAPHICS_GPIO0_1V8 */
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26
>;
};
pinctrl_hog_misc: hog-misc-grp {
fsl,pins = <
/* ENET_WOL# -- shared by both PHYs */
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090
/* PG_V_IN_VAR# */
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
/* CSI2_PD_1V8 */
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
/* CSI2_RESET_1V8# */
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
/* DIS_USB_DN1 */
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
/* DIS_USB_DN2 */
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0
/* EEPROM_WP_1V8# */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100
/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0
/* GRAPHICS_PRSNT_1V8# */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
/* CLK_CCM_CLKO1_3V3 */
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
>;
};
pinctrl_hog_sbc: hog-sbc-grp {
fsl,pins = <
/* MEMCFG[0..2] straps */
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84
>;
};
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
>;
};
pinctrl_i2c3_gpio: i2c3-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
>;
};
pinctrl_i2c5: i2c5-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
>;
};
pinctrl_i2c5_gpio: i2c5-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
>;
};
pinctrl_panel_backlight: panel-backlight-grp {
fsl,pins = <
/* BL_ENABLE_1V8 */
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104
>;
};
pinctrl_panel_expansion: panel-expansion-grp {
fsl,pins = <
/* DSI_RESET_1V8# */
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2
/* DSI_IRQ_1V8# */
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090
>;
};
pinctrl_panel_pwm: panel-pwm-grp {
fsl,pins = <
/* BL_PWM_3V3 */
MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12
>;
};
pinctrl_panel_vcc_reg: panel-vcc-grp {
fsl,pins = <
/* TFT_ENABLE_1V8 */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104
>;
};
pinctrl_pcie0: pcie-grp {
fsl,pins = <
/* M2_PCIE_RST# */
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
/* M2_W_DISABLE1_1V8# */
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
/* M2_W_DISABLE2_1V8# */
MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
/* CLK_M2_32K768 */
MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
/* M2_PCIE_WAKE# */
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
/* M2_PCIE_CLKREQ# */
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61
>;
};
pinctrl_pdm: pdm-grp {
fsl,pins = <
/* PDM_SEL */
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0
MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0
MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0
>;
};
pinctrl_pmic: pmic-grp {
fsl,pins = <
/* PMIC_nINT */
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
>;
};
pinctrl_rtc: rtc-grp {
fsl,pins = <
/* RTC_IRQ# */
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090
>;
};
pinctrl_sai1: sai1-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6
MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6
>;
};
pinctrl_sai2: sai2-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
>;
};
pinctrl_sai3: sai3-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49
MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49
MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49
MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
>;
};
pinctrl_uart2: uart2-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49
MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49
MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
>;
};
pinctrl_uart3: uart3-grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
>;
};
pinctrl_uart4: uart4-grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
>;
};
pinctrl_usdhc3: usdhc3-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
>;
};
pinctrl_usb_hub: usb-hub-grp {
fsl,pins = <
/* USBHUB_RESET# */
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4
>;
};
pinctrl_usb1: usb1-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80
>;
};
pinctrl_watchdog_gpio: watchdog-gpio-grp {
fsl,pins = <
/* WDOG_B# */
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26
/* WDOG_EN -- ungate WDT RESET# signal propagation */
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6
/* WDOG_KICK# / WDI */
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26
>;
};
};

59
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
Просмотреть файл

@ -43,6 +43,17 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_hub: regulator-usb-hub {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_hub>;
regulator-name = "USB_HUB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
@ -254,6 +265,41 @@
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
dr_mode = "host";
status = "okay";
/* 2.x hub on port 1 */
usb_hub_2_x: hub@1 {
compatible = "usbbda,5411";
reg = <1>;
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_usb_hub>;
peer-hub = <&usb_hub_3_x>;
};
/* 3.x hub on port 2 */
usb_hub_3_x: hub@2 {
compatible = "usbbda,411";
reg = <2>;
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_usb_hub>;
peer-hub = <&usb_hub_2_x>;
};
};
/* SD Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@ -384,6 +430,12 @@
>;
};
pinctrl_reg_usb_hub: regusbhubgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x19
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
@ -411,6 +463,13 @@
>;
};
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190

30
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts
Просмотреть файл

@ -104,20 +104,10 @@
};
};
/*
* PDK2 carrier board uses SoM with KSZ9131 populated and connected to
* SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
*/
/delete-node/ &ethphy0f;
/*
* PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
* ethernet RGMII interface. The SoM is not populated with second FEC PHY.
*/
/delete-node/ &ethphy1f;
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rgmii>;
phy-handle = <&ethphypdk>;
phy-mode = "rgmii";
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
@ -151,6 +141,20 @@
status = "okay";
};
&pcie_phy {
clock-names = "ref";
clocks = <&clk IMX8MP_SYS_PLL2_100M>;
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_UNUSED>;
status = "okay";
};
&pcie {
fsl,max-link-speed = <1>;
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; /* GPIO J */
status = "okay";
};
&usb3_1 {
fsl,over-current-active-low;
};
@ -159,7 +163,7 @@
/*
* GPIO_A,B,C,D are connected to buttons.
* GPIO_E,F,H,I are connected to LEDs.
* GPIO_M is connected to CLKOUT2.
* GPIO_M is connected to CLKOUT1.
*/
pinctrl-0 = <&pinctrl_hog_base
&pinctrl_dhcom_g &pinctrl_dhcom_j

306
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts Normal file
Просмотреть файл

@ -0,0 +1,306 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Marek Vasut <marex@denx.de>
*
* DHCOM iMX8MP variant:
* DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
* DHCOM PCB number: 660-100 or newer
* PDK3 PCB number: 669-100 or newer
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-dhcom-som.dtsi"
/ {
model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)";
compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
"fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
clk_pcie: clock-pcie {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_c_0_hs_ep: endpoint {
remote-endpoint = <&dwc3_0_hs_ep>;
};
};
port@1 {
reg = <1>;
usb_c_0_ss_ep: endpoint {
remote-endpoint = <&ptn5150_in_ep>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
button-0 {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
label = "TA1-GPIO-A";
linux,code = <KEY_A>;
pinctrl-0 = <&pinctrl_dhcom_a>;
pinctrl-names = "default";
wakeup-source;
};
button-1 {
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
label = "TA2-GPIO-B";
linux,code = <KEY_B>;
pinctrl-0 = <&pinctrl_dhcom_b>;
pinctrl-names = "default";
wakeup-source;
};
button-2 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
label = "TA3-GPIO-C";
linux,code = <KEY_C>;
pinctrl-0 = <&pinctrl_dhcom_c>;
pinctrl-names = "default";
wakeup-source;
};
button-3 {
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; /* GPIO E */
label = "TA4-GPIO-E";
linux,code = <KEY_E>;
pinctrl-0 = <&pinctrl_dhcom_e>;
pinctrl-names = "default";
wakeup-source;
};
};
led {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <0>;
gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; /* GPIO D */
pinctrl-0 = <&pinctrl_dhcom_d>;
pinctrl-names = "default";
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
pinctrl-0 = <&pinctrl_dhcom_f>;
pinctrl-names = "default";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */
pinctrl-0 = <&pinctrl_dhcom_g>;
pinctrl-names = "default";
};
led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
pinctrl-0 = <&pinctrl_dhcom_i>;
pinctrl-names = "default";
};
};
reg_avdd: regulator-avdd { /* AUDIO_VDD */
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "AUDIO_VDD";
};
};
&i2c5 {
i2c-mux@70 {
compatible = "nxp,pca9540";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2cmuxed0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&gpio4>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ptn5150_in_ep: endpoint {
remote-endpoint = <&usb_c_0_ss_ep>;
};
};
port@1 {
reg = <1>;
ptn5150_out_ep: endpoint {
remote-endpoint = <&dwc3_0_ss_ep>;
};
};
};
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <20000>; /* 0.02 R */
ti,shunt-gain = <1>; /* Drop cca. 40mV */
};
eeprom_board: eeprom@54 {
compatible = "atmel,24c04";
pagesize = <16>;
reg = <0x54>;
};
};
i2cmuxed1: i2c@1 { /* HDMI DDC I2C */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
&ethphy0g {
reg = <7>;
};
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rgmii>;
phy-handle = <&ethphypdk>;
phy-mode = "rgmii-id";
mdio {
ethphypdk: ethernet-phy@7 { /* Micrel KSZ9131RNXI */
compatible = "ethernet-phy-id0022.1642",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
reg = <7>;
reset-assert-us = <1000>;
/* RESET_N signal rise time ~100ms */
reset-deassert-us = <120000>;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
};
};
};
&flexcan1 {
status = "okay";
};
&pcie_phy {
clocks = <&clk_pcie>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
status = "okay";
};
&pcie {
fsl,max-link-speed = <3>;
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb_dwc3_0 {
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_hs_ep: endpoint@0 {
reg = <0>;
remote-endpoint = <&usb_c_0_hs_ep>;
};
dwc3_0_ss_ep: endpoint@1 {
reg = <1>;
remote-endpoint = <&ptn5150_out_ep>;
};
};
};
&usb3_1 {
fsl,disable-port-power-control;
fsl,permanently-attached;
};
&usb_dwc3_1 {
/* This port has USB5734 Hub connected to it, PWR/OC pins are unused */
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
};
&iomuxc {
/*
* GPIO_A,B,C,E are connected to buttons.
* GPIO_D,F,G,I are connected to LEDs.
* GPIO_H is connected to USB Hub RESET_N.
* GPIO_M is connected to CLKOUT2.
*/
pinctrl-0 = <&pinctrl_hog_base
&pinctrl_dhcom_h &pinctrl_dhcom_j &pinctrl_dhcom_k
&pinctrl_dhcom_l
&pinctrl_dhcom_int>;
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000
>;
};
};

52
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
Просмотреть файл

@ -83,7 +83,7 @@
&eqos { /* First ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-0 = <&pinctrl_eqos_rgmii>;
phy-handle = <&ethphy0g>;
phy-mode = "rgmii-id";
status = "okay";
@ -94,14 +94,14 @@
#size-cells = <0>;
/* Up to one of these two PHYs may be populated. */
ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <1>;
reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
@ -129,9 +129,9 @@
&fec { /* Second ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-0 = <&pinctrl_fec_rmii>;
phy-handle = <&ethphy1f>;
phy-mode = "rgmii";
phy-mode = "rmii";
fsl,magic-packet;
status = "okay";
@ -547,7 +547,7 @@
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
/* GPIO_M is connected to CLKOUT2 */
/* GPIO_M is connected to CLKOUT1 */
&pinctrl_dhcom_int>;
pinctrl-names = "default";
@ -673,7 +673,7 @@
>;
};
pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
@ -692,6 +692,22 @@
>;
};
pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
/* Clock */
MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f
>;
};
pinctrl_enet_vio: dhcom-enet-vio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
@ -700,9 +716,9 @@
pinctrl_ethphy0: dhcom-ethphy0-grp {
fsl,pins = <
/* ENET1_#RST Reset */
/* ENET_QOS_#RST Reset */
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
/* ENET1_#INT Interrupt */
/* ENET_QOS_#INT Interrupt */
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
>;
};
@ -716,7 +732,7 @@
>;
};
pinctrl_fec: dhcom-fec-grp {
pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
@ -737,6 +753,22 @@
>;
};
pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
/* Clock */
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f
>;
};
pinctrl_flexcan1: dhcom-flexcan1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154

2
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
Просмотреть файл

@ -80,12 +80,14 @@
label = "S12";
linux,code = <BTN_0>;
gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
wakeup-source;
};
switch-2 {
label = "S13";
linux,code = <BTN_1>;
gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};

9
arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
Просмотреть файл

@ -67,7 +67,14 @@
/* TODO: Audio Codec */
};
/* TODO: Verdin PCIE_1 */
/* Verdin PCIE_1 */
&pcie {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin PWM_1 */
&pwm1 {

9
arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
Просмотреть файл

@ -91,7 +91,14 @@
/* TODO: Audio Codec */
};
/* TODO: Verdin PCIE_1 */
/* Verdin PCIE_1 */
&pcie {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin PWM_1 */
&pwm1 {

5
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi
Просмотреть файл

@ -65,6 +65,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_uart>;
status = "okay";
bluetooth {
compatible = "mrvl,88w8997";
max-speed = <921600>;
};
};
/* On-module Wi-Fi */

5
arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
Просмотреть файл

@ -87,7 +87,7 @@
status = "okay";
};
/* EEPROM on Verdin yavia board */
/* EEPROM on Verdin Yavia board */
&eeprom_carrier_board {
status = "okay";
};
@ -122,7 +122,7 @@
status = "okay";
};
&pcie_phy{
&pcie_phy {
status = "okay";
};
@ -183,7 +183,6 @@
};
&usb_dwc3_1 {
disable-over-current;
status = "okay";
};

15
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
Просмотреть файл

@ -748,7 +748,20 @@
};
};
/* TODO: Verdin PCIE_1 */
/* Verdin PCIE_1 */
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
/* PCIE_1_RESET# (SODIMM 244) */
reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
&pcie_phy {
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
};
/* Verdin PWM_1 */
&pwm1 {

135
arch/arm64/boot/dts/freescale/imx8mp.dtsi
Просмотреть файл

@ -409,6 +409,30 @@
status = "disabled";
};
gpt1: timer@302d0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
clock-names = "ipg", "per";
};
gpt2: timer@302e0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
clock-names = "ipg", "per";
};
gpt3: timer@302f0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
clock-names = "ipg", "per";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mp-iomuxc";
reg = <0x30330000 0x10000>;
@ -722,6 +746,30 @@
clocks = <&osc_24m>;
clock-names = "per";
};
gpt6: timer@306e0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x306e0000 0x10000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
clock-names = "ipg", "per";
};
gpt5: timer@306f0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x306f0000 0x10000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
clock-names = "ipg", "per";
};
gpt4: timer@30700000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x30700000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
clock-names = "ipg", "per";
};
};
aips3: bus@30800000 {
@ -1126,6 +1174,61 @@
#size-cells = <1>;
ranges;
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <200000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif1: endpoint {
remote-endpoint = <&lcdif1_to_dsim>;
};
};
};
};
lcdif1: display-controller@32e80000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32e80000 0x10000>;
clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <594000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
status = "disabled";
port {
lcdif1_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif1>;
};
};
};
lcdif2: display-controller@32e90000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32e90000 0x238>;
@ -1151,7 +1254,7 @@
media_blk_ctrl: blk-ctrl@32ec0000 {
compatible = "fsl,imx8mp-media-blk-ctrl",
"simple-bus", "syscon";
"syscon";
reg = <0x32ec0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
@ -1202,10 +1305,10 @@
lvds_bridge: bridge@5c {
compatible = "fsl,imx8mp-ldb";
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
clock-names = "ldb";
reg = <0x5c 0x4>, <0x128 0x4>;
reg-names = "ldb", "lvds";
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
clock-names = "ldb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
status = "disabled";
@ -1309,6 +1412,32 @@
status = "disabled";
};
pcie_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mp-pcie-ep";
reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
reg-names = "dbi", "addr_space";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
interrupt-names = "dma";
fsl,max-link-speed = <3>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
status = "disabled";
};
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
Просмотреть файл

@ -667,7 +667,7 @@
>;
};
pinctrl_spkamp: spkamp {
pinctrl_spkamp: spkampgrp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */
>;

14
arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts
Просмотреть файл

@ -12,18 +12,16 @@
compatible = "purism,librem5r2", "purism,librem5", "fsl,imx8mq";
};
&bq25895 {
ti,battery-regulation-voltage = <4192000>; /* uV */
ti,charge-current = <1600000>; /* uA */
ti,termination-current = <66000>; /* uA */
};
&accel_gyro {
mount-matrix = "1", "0", "0",
"0", "-1", "0",
"0", "0", "1";
};
&proximity {
proximity-near-level = <120>;
&bq25895 {
ti,charge-current = <1600000>; /* uA */
};
&proximity {
proximity-near-level = <50>;
};

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
Просмотреть файл

@ -7,7 +7,7 @@
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <1000000>;
opp-microvolt = <950000>;
};
};

12
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi
Просмотреть файл

@ -22,9 +22,7 @@
};
&bq25895 {
ti,battery-regulation-voltage = <4200000>; /* uV */
ti,charge-current = <1500000>; /* uA */
ti,termination-current = <144000>; /* uA */
};
&camera_front {
@ -40,6 +38,12 @@
};
};
&proximity {
proximity-near-level = <25>;
&magnetometer {
mount-matrix = "1", "0", "0",
"0", "-1", "0",
"0", "0", "-1";
};
&proximity {
proximity-near-level = <10>;
};

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts
Просмотреть файл

@ -23,5 +23,5 @@
};
&proximity {
proximity-near-level = <10>;
proximity-near-level = <5>;
};

79
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
Просмотреть файл

@ -20,6 +20,8 @@
backlight_dsi: backlight-dsi {
compatible = "led-backlight";
leds = <&led_backlight>;
brightness-levels = <255>;
default-brightness-level = <190>;
};
pmic_osc: clock-pmic {
@ -84,13 +86,21 @@
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audiopwr>;
regulator-name = "AUDIO_PWR_EN";
regulator-name = "AUD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_mic_2v4: regulator-mic-2v4 {
compatible = "regulator-fixed";
regulator-name = "MIC_2V4";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2400000>;
vin-supply = <&reg_aud_1v8>;
};
/*
* the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC
* since we can't have it twice in the 2 different regulator nodes.
@ -319,6 +329,10 @@
opp-hz = /bits/ 64 <100000000>;
};
opp-166000000 {
opp-hz = /bits/ 64 <166935483>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
};
@ -371,6 +385,16 @@
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
/* CLKO2 for cameras on both CSI1 and CSI2 */
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
>;
};
pinctrl_audiopwr: audiopwrgrp {
fsl,pins = <
/* AUDIO_POWER_EN_3V3 */
@ -662,7 +686,7 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
@ -679,7 +703,7 @@
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
@ -709,7 +733,7 @@
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
@ -722,7 +746,7 @@
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
@ -758,7 +782,7 @@
};
&i2c1 {
clock-frequency = <387000>;
clock-frequency = <384000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
@ -806,6 +830,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>;
clocks = <&pmic_osc>;
#clock-cells = <0>;
clock-names = "osc";
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
@ -819,9 +844,9 @@
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <800000>;
rohm,dvs-run-voltage = <880000>;
rohm,dvs-idle-voltage = <820000>;
rohm,dvs-suspend-voltage = <810000>;
regulator-always-on;
};
@ -831,8 +856,8 @@
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
rohm,dvs-run-voltage = <950000>;
rohm,dvs-idle-voltage = <850000>;
regulator-always-on;
};
@ -841,14 +866,14 @@
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-run-voltage = <850000>;
};
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-run-voltage = <930000>;
};
buck5_reg: BUCK5 {
@ -956,12 +981,12 @@
};
&i2c2 {
clock-frequency = <387000>;
clock-frequency = <384000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
magnetometer@1e {
magnetometer: magnetometer@1e {
compatible = "st,lsm9ds1-magn";
reg = <0x1e>;
pinctrl-names = "default";
@ -1005,7 +1030,7 @@
};
&i2c3 {
clock-frequency = <387000>;
clock-frequency = <384000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
@ -1023,7 +1048,7 @@
DBVDD-supply = <&reg_aud_1v8>;
AVDD-supply = <&reg_aud_1v8>;
CPVDD-supply = <&reg_aud_1v8>;
MICVDD-supply = <&reg_aud_1v8>;
MICVDD-supply = <&reg_mic_2v4>;
PLLVDD-supply = <&reg_aud_1v8>;
SPKVDD1-supply = <&reg_vsys_3v4>;
SPKVDD2-supply = <&reg_vsys_3v4>;
@ -1095,7 +1120,7 @@
};
&i2c4 {
clock-frequency = <387000>;
clock-frequency = <384000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
@ -1127,7 +1152,9 @@
interrupt-parent = <&gpio3>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
phys = <&usb3_phy0>;
ti,precharge-current = <130000>; /* uA */
ti,battery-regulation-voltage = <4208000>; /* uV */
ti,termination-current = <128000>; /* uA */
ti,precharge-current = <128000>; /* uA */
ti,minimum-sys-voltage = <3700000>; /* uV */
ti,boost-voltage = <5000000>; /* uV */
ti,boost-max-current = <1500000>; /* uA */
@ -1143,6 +1170,7 @@
};
&mipi_csi1 {
assigned-clock-rates = <266000000>, <200000000>, <66000000>;
status = "okay";
ports {
@ -1299,7 +1327,6 @@
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "otg";
snps,dis_u3_susphy_quirk;
usb-role-switch;
status = "okay";
@ -1366,7 +1393,7 @@
mmc-pwrseq = <&usdhc2_pwrseq>;
post-power-on-delay-ms = <1000>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
max-frequency = <50000000>;
max-frequency = <100000000>;
disable-wp;
cap-sdio-irq;
keep-power-in-suspend;
@ -1380,3 +1407,13 @@
fsl,ext-reset-output;
status = "okay";
};
&a53_opp_table {
opp-1000000000 {
opp-microvolt = <850000>;
};
opp-1500000000 {
opp-microvolt = <950000>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
Просмотреть файл

@ -169,8 +169,6 @@
hnp-disable;
srp-disable;
adp-disable;
/* OC not supported due to non matching active polarity */
disable-over-current;
dr_mode = "otg";
status = "okay";
};

40
arch/arm64/boot/dts/freescale/imx8mq.dtsi
Просмотреть файл

@ -940,6 +940,8 @@
clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
<&clk IMX8MQ_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -951,6 +953,8 @@
clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
<&clk IMX8MQ_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -962,6 +966,8 @@
clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
<&clk IMX8MQ_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1157,6 +1163,8 @@
clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
<&clk IMX8MQ_CLK_UART4_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1605,6 +1613,38 @@
status = "disabled";
};
pcie1_ep: pcie-ep@33c00000 {
compatible = "fsl,imx8mq-pcie-ep";
reg = <0x33c00000 0x000400000>,
<0x20000000 0x08000000>;
reg-names = "dbi", "addr_space";
num-lanes = <1>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
fsl,max-link-speed = <2>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
num-ib-windows = <4>;
num-ob-windows = <4>;
status = "disabled";
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */

16
arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8qm-apalis.dtsi"
#include "imx8-apalis-eval.dtsi"
/ {
model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board";
compatible = "toradex,apalis-imx8-eval",
"toradex,apalis-imx8",
"fsl,imx8qm";
};

16
arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8qm-apalis.dtsi"
#include "imx8-apalis-ixora-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM/QP on Apalis Ixora V1.1 Carrier Board";
compatible = "toradex,apalis-imx8-ixora-v1.1",
"toradex,apalis-imx8",
"fsl,imx8qm";
};

16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8qm-apalis-v1.1.dtsi"
#include "imx8-apalis-eval.dtsi"
/ {
model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board";
compatible = "toradex,apalis-imx8-v1.1-eval",
"toradex,apalis-imx8-v1.1",
"fsl,imx8qm";
};

16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8qm-apalis-v1.1.dtsi"
#include "imx8-apalis-ixora-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.1 Carrier Board";
compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1",
"toradex,apalis-imx8-v1.1",
"fsl,imx8qm";
};

16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include "imx8qm-apalis-v1.1.dtsi"
#include "imx8-apalis-ixora-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.2 Carrier Board";
compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2",
"toradex,apalis-imx8-v1.1",
"fsl,imx8qm";
};

16
arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include <dt-bindings/pwm/pwm.h>
#include "imx8qm.dtsi"
#include "imx8-apalis-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM V1.1";
compatible = "toradex,apalis-imx8-v1.1",
"fsl,imx8qm";
};
/* TODO: Cooling Maps */

340
arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi Normal file
Просмотреть файл

@ -0,0 +1,340 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
#include "imx8qm-apalis-v1.1.dtsi"
/ {
model = "Toradex Apalis iMX8QM";
compatible = "toradex,apalis-imx8",
"fsl,imx8qm";
};
&ethphy0 {
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
};
/*
* Apalis iMX8QM V1.0 has PHY KSZ9031. the Micrel PHY driver
* doesn't support setting internal PHY delay for TXC line for
* this PHY model. Use delay on MAC side instead.
*/
&fec1 {
fsl,rgmii_txc_dly;
phy-mode = "rgmii-rxid";
};
/* TODO: Apalis HDMI1 */
/* Apalis I2C2 (DDC) */
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c0>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
};
&lsio_gpio0 {
gpio-line-names = "MXM3_279",
"MXM3_277",
"MXM3_135",
"MXM3_203",
"MXM3_201",
"MXM3_275",
"MXM3_110",
"MXM3_120",
"MXM3_1/GPIO1",
"MXM3_3/GPIO2",
"MXM3_124",
"MXM3_122",
"MXM3_5/GPIO3",
"MXM3_7/GPIO4",
"",
"",
"MXM3_4",
"MXM3_211",
"MXM3_209",
"MXM3_2",
"MXM3_136",
"MXM3_134",
"MXM3_6",
"MXM3_8",
"MXM3_112",
"MXM3_118",
"MXM3_114",
"MXM3_116";
};
&lsio_gpio1 {
gpio-line-names = "",
"",
"",
"",
"MXM3_286",
"",
"MXM3_87",
"MXM3_99",
"MXM3_138",
"MXM3_140",
"MXM3_239",
"",
"MXM3_281",
"MXM3_283",
"MXM3_126",
"MXM3_132",
"",
"",
"",
"",
"MXM3_173",
"MXM3_175",
"MXM3_123";
};
&lsio_gpio2 {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"MXM3_198",
"MXM3_35",
"MXM3_164",
"",
"",
"",
"",
"MXM3_217",
"MXM3_215",
"",
"",
"MXM3_193",
"MXM3_194",
"MXM3_37",
"",
"MXM3_271",
"MXM3_273",
"MXM3_195",
"MXM3_197",
"MXM3_177",
"MXM3_179",
"MXM3_181",
"MXM3_183",
"MXM3_185",
"MXM3_187";
};
&lsio_gpio3 {
gpio-line-names = "MXM3_191",
"",
"MXM3_221",
"MXM3_225",
"MXM3_223",
"MXM3_227",
"MXM3_200",
"MXM3_235",
"MXM3_231",
"MXM3_229",
"MXM3_233",
"MXM3_204",
"MXM3_196",
"",
"MXM3_202",
"",
"",
"",
"MXM3_305",
"MXM3_307",
"MXM3_309",
"MXM3_311",
"MXM3_315",
"MXM3_317",
"MXM3_319",
"MXM3_321",
"MXM3_15/GPIO7",
"MXM3_63",
"MXM3_17/GPIO8",
"MXM3_12",
"MXM3_14",
"MXM3_16";
};
&lsio_gpio4 {
gpio-line-names = "MXM3_18",
"MXM3_11/GPIO5",
"MXM3_13/GPIO6",
"MXM3_274",
"MXM3_84",
"MXM3_262",
"MXM3_96",
"",
"",
"",
"",
"",
"MXM3_190",
"",
"",
"",
"MXM3_269",
"MXM3_251",
"MXM3_253",
"MXM3_295",
"MXM3_299",
"MXM3_301",
"MXM3_297",
"MXM3_293",
"MXM3_291",
"MXM3_289",
"MXM3_287";
/* Enable pcie root / sata ref clock unconditionally */
pcie-sata-hog {
gpios = <27 GPIO_ACTIVE_HIGH>;
};
};
&lsio_gpio5 {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"MXM3_150",
"MXM3_160",
"MXM3_162",
"MXM3_144",
"MXM3_146",
"MXM3_148",
"MXM3_152",
"MXM3_156",
"MXM3_158",
"MXM3_159",
"MXM3_184",
"MXM3_180",
"MXM3_186",
"MXM3_188",
"MXM3_176",
"MXM3_178";
};
&lsio_gpio6 {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"MXM3_261",
"MXM3_263",
"MXM3_259",
"MXM3_257",
"MXM3_255",
"MXM3_128",
"MXM3_130",
"MXM3_265",
"MXM3_249",
"MXM3_247",
"MXM3_245",
"MXM3_243";
};
&pinctrl_fec1 {
fsl,pins =
/* Use pads in 1.8V mode */
<IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
<IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
<IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
<IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>,
<IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>,
<IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>,
<IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>,
<IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020>,
<IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020>,
<IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020>,
<IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020>,
<IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020>,
<IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020>,
<IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020>,
<IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020>,
<IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020>,
/* On-module ETH_RESET# */
<IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>,
/* On-module ETH_INT# */
<IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000060>;
};
&pinctrl_fec1_sleep {
fsl,pins =
<IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
<IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040>,
<IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040>,
<IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040>,
<IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040>,
<IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040>,
<IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040>,
<IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040>,
<IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040>,
<IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040>,
<IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040>,
<IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040>,
<IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040>,
<IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040>,
<IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040>,
<IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040>,
<IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040>,
<IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000040>;
};
&iomuxc {
/* Apalis I2C2 (DDC) */
pinctrl_lpi2c0: lpi2c0grp {
fsl,pins =
<IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022>,
<IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022>;
};
};
/* On-module PCIe_CTRL0_CLKREQ */
&pinctrl_pcie_sata_refclk {
fsl,pins =
<IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021>;
};
/* TODO: On-module Wi-Fi */
/* Apalis MMC1 */
&usdhc2 {
/*
* The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
* issues with certain SD cards, disable 1.8V signaling for now.
*/
no-1-8-v;
};
/* Apalis SD1 */
&usdhc3 {
/*
* The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
* issues with certain SD cards, disable 1.8V signaling for now.
*/
no-1-8-v;
};

44
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
Просмотреть файл

@ -16,6 +16,50 @@
"uart4_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_4>;
};
can1_lpcg: clock-controller@5ace0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ace0000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>, <&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
clock-output-names = "can1_lpcg_pe_clk",
"can1_lpcg_ipg_clk",
"can1_lpcg_chi_clk";
power-domains = <&pd IMX_SC_R_CAN_1>;
};
can2_lpcg: clock-controller@5acf0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5acf0000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>, <&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
clock-output-names = "can2_lpcg_pe_clk",
"can2_lpcg_ipg_clk",
"can2_lpcg_chi_clk";
power-domains = <&pd IMX_SC_R_CAN_2>;
};
};
&flexcan1 {
fsl,clk-source = /bits/ 8 <1>;
};
&flexcan2 {
clocks = <&can1_lpcg 1>,
<&can1_lpcg 0>;
assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
fsl,clk-source = /bits/ 8 <1>;
};
&flexcan3 {
clocks = <&can2_lpcg 1>,
<&can2_lpcg 0>;
assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
fsl,clk-source = /bits/ 8 <1>;
};
&lpuart0 {

4
arch/arm64/boot/dts/freescale/imx8qm.dtsi
Просмотреть файл

@ -23,6 +23,9 @@
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
vpu_core0 = &vpu_core0;
vpu_core1 = &vpu_core1;
vpu_core2 = &vpu_core2;
};
cpus {
@ -212,6 +215,7 @@
};
/* sorted in register address */
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"

16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8qxp-colibri.dtsi"
#include "imx8x-colibri-aster.dtsi"
/ {
model = "Toradex Colibri iMX8QXP on Aster Board";
compatible = "toradex,colibri-imx8x-aster",
"toradex,colibri-imx8x",
"fsl,imx8qxp";
};

6
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
Просмотреть файл

@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
@ -6,10 +6,10 @@
/dts-v1/;
#include "imx8qxp-colibri.dtsi"
#include "imx8qxp-colibri-eval-v3.dtsi"
#include "imx8x-colibri-eval-v3.dtsi"
/ {
model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";
model = "Toradex Colibri iMX8QXP on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx8x-eval-v3",
"toradex,colibri-imx8x", "fsl,imx8qxp";
};

62
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
Просмотреть файл

@ -1,62 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2019 Toradex
*/
#include <dt-bindings/input/linux-event-codes.h>
/ {
aliases {
rtc0 = &rtc_i2c;
rtc1 = &rtc;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
key-wakeup {
label = "Wake-Up";
gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
debounce-interval = <10>;
wakeup-source;
};
};
};
&i2c1 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/* Colibri UART_B */
&lpuart0 {
status = "okay";
};
/* Colibri UART_C */
&lpuart2 {
status = "okay";
};
/* Colibri UART_A */
&lpuart3 {
status = "okay";
};
/* Colibri FastEthernet */
&fec1 {
status = "okay";
};
/* Colibri SD/MMC Card */
&usdhc2 {
status = "okay";
};

16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8qxp-colibri.dtsi"
#include "imx8x-colibri-iris-v2.dtsi"
/ {
model = "Toradex Colibri iMX8QXP on Colibri Iris V2 Board";
compatible = "toradex,colibri-imx8x-iris-v2",
"toradex,colibri-imx8x",
"fsl,imx8qxp";
};

16
arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts Normal file
Просмотреть файл

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8qxp-colibri.dtsi"
#include "imx8x-colibri-iris.dtsi"
/ {
model = "Toradex Colibri iMX8QXP on Colibri Iris Board";
compatible = "toradex,colibri-imx8x-iris",
"toradex,colibri-imx8x",
"fsl,imx8qxp";
};

592
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
Просмотреть файл

@ -1,598 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
#include "imx8qxp.dtsi"
#include "imx8x-colibri.dtsi"
/ {
model = "Toradex Colibri iMX8QXP/DX Module";
model = "Toradex Colibri iMX8QXP Module";
compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
chosen {
stdout-path = &lpuart3;
};
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
/* On-module I2C */
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
status = "okay";
/* Touch controller */
touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ad7879_int>;
reg = <0x2c>;
interrupt-parent = <&lsio_gpio3>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
touchscreen-max-pressure = <4096>;
adi,resistance-plate-x = <120>;
adi,first-conversion-delay = /bits/ 8 <3>;
adi,acquisition-time = /bits/ 8 <1>;
adi,median-filter-size = /bits/ 8 <2>;
adi,averaging = /bits/ 8 <1>;
adi,conversion-interval = /bits/ 8 <255>;
};
};
/* Colibri I2C */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
};
/* Colibri UART_B */
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
};
/* Colibri UART_C */
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
};
/* Colibri UART_A */
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};
/* Colibri FastEthernet */
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
reg = <2>;
};
};
};
/* On-module eMMC */
&usdhc1 {
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
status = "okay";
};
/* Colibri SD/MMC Card */
&usdhc2 {
bus-width = <4>;
cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_module_3v3>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
disable-wp;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
/* On-module touch pen-down interrupt */
pinctrl_ad7879_int: ad7879intgrp {
fsl,pins = <
IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21
>;
};
/* Colibri Analogue Inputs */
pinctrl_adc0: adc0grp {
fsl,pins = <
IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */
IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */
IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */
IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */
>;
};
pinctrl_can_int: canintgrp {
fsl,pins = <
IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */
>;
};
pinctrl_csi_ctl: csictlgrp {
fsl,pins = <
IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */
IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */
>;
};
pinctrl_ext_io0: extio0grp {
fsl,pins = <
IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */
>;
};
/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61
>;
};
pinctrl_fec1_sleep: fec1slpgrp {
fsl,pins = <
IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041
IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041
IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41
IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41
IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41
IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41
IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41
IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41
IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41
IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41
>;
};
/* Colibri optional CAN on UART_B RTS/CTS */
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <
IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */
IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */
>;
};
/* Colibri optional CAN on PS2 */
pinctrl_flexcan2: flexcan1grp {
fsl,pins = <
IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */
IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */
>;
};
/* Colibri optional CAN on UART_A TXD/RXD */
pinctrl_flexcan3: flexcan2grp {
fsl,pins = <
IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */
IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */
>;
};
/* Colibri LCD Back-Light GPIO */
pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */
>;
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */
>;
};
pinctrl_hog0: hog0grp {
fsl,pins = <
IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */
IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */
IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */
IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */
IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */
IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */
IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */
IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */
IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */
IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */
IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */
IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */
IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */
IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */
IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */
IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */
IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */
IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */
IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */
IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */
IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */
IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */
IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */
IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */
IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */
IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */
>;
};
pinctrl_hog1: hog1grp {
fsl,pins = <
IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */
IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */
>;
};
/*
* This pin is used in the SCFW as a UART. Using it from
* Linux would require rewritting the SCFW board file.
*/
pinctrl_hog_scfw: hogscfwgrp {
fsl,pins = <
IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */
>;
};
/* On Module I2C */
pinctrl_i2c0: i2c0grp {
fsl,pins = <
IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
>;
};
/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
fsl,pins = <
IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */
IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */
>;
};
/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
fsl,pins = <
IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */
IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */
>;
};
/* Colibri I2C */
pinctrl_i2c1: i2c1grp {
fsl,pins = <
IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */
IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */
>;
};
/* Colibri Parallel RGB LCD Interface */
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */
IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */
IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */
IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */
IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */
IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */
IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */
IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */
IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */
IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */
IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */
IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */
IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */
IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */
IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */
IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */
IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */
IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */
IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */
IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */
IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */
IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */
IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */
IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */
IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */
>;
};
/* Colibri SPI */
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */
IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */
IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */
IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */
>;
};
/* Colibri UART_B */
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */
IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */
IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */
IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */
>;
};
/* Colibri UART_C */
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */
IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */
>;
};
/* Colibri UART_A */
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */
IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */
>;
};
/* Colibri UART_A Control */
pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
fsl,pins = <
IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */
IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */
IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */
IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */
IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */
IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
>;
};
/* On module wifi module */
pinctrl_pcieb: pciebgrp {
fsl,pins = <
IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */
IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */
IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */
>;
};
/* Colibri PWM_A */
pinctrl_pwm_a: pwmagrp {
/* both pins are connected together, reserve the unused CSI_D05 */
fsl,pins = <
IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */
IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */
>;
};
/* Colibri PWM_B */
pinctrl_pwm_b: pwmbgrp {
fsl,pins = <
IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */
>;
};
/* Colibri PWM_C */
pinctrl_pwm_c: pwmcgrp {
fsl,pins = <
IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */
>;
};
/* Colibri PWM_D */
pinctrl_pwm_d: pwmdgrp {
/* both pins are connected together, reserve the unused CSI_D04 */
fsl,pins = <
IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */
IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */
>;
};
/* On-module I2S */
pinctrl_sai0: sai0grp {
fsl,pins = <
IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040
IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040
IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040
IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
>;
};
/* Colibri Audio Analogue Microphone GND */
pinctrl_sgtl5000: sgtl5000grp {
fsl,pins = <
/* MIC GND EN */
IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41
>;
};
/* On-module SGTL5000 clock */
pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
fsl,pins = <
IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21
>;
};
/* On-module USB interrupt */
pinctrl_usb3503a: usb3503agrp {
fsl,pins = <
IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61
>;
};
/* Colibri USB Client Cable Detect */
pinctrl_usbc_det: usbcdetgrp {
fsl,pins = <
IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */
>;
};
/* USB Host Power Enable */
pinctrl_usbh1_reg: usbh1reggrp {
fsl,pins = <
IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */
>;
};
/* On-module eMMC */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
>;
};
/* Colibri SD/MMC Card Detect */
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */
>;
};
/* Colibri SD/MMC Card */
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
>;
};
pinctrl_usdhc2_sleep: usdhc2slpgrp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */
IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */
IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */
IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */
IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */
IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20
>;
};
};

87
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
Просмотреть файл

@ -6,6 +6,7 @@
/dts-v1/;
#include "imx8qxp.dtsi"
#include <dt-bindings/usb/pd.h>
/ {
model = "Freescale i.MX8QXP MEK";
@ -28,6 +29,21 @@
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
gpio-sbu-mux {
compatible = "gpio-sbu-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec_mux>;
select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
orientation-switch;
port {
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
};
&dsp {
@ -127,6 +143,42 @@
};
};
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x50>;
interrupt-parent = <&lsio_gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
port {
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
usb_con1: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "source";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
};
&lpuart0 {
@ -148,7 +200,7 @@
};
&thermal_zones {
pmic-thermal0 {
pmic-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
@ -204,6 +256,27 @@
status = "okay";
};
&usb3_phy {
status = "okay";
};
&usbotg3 {
status = "okay";
};
&usbotg3_cdns3 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
};
&vpu {
compatible = "nxp,imx8qxp-vpu";
status = "okay";
@ -267,6 +340,18 @@
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
>;
};
pinctrl_typec_mux: typecmuxgrp {
fsl,pins = <
IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041

44
arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi Normal file
Просмотреть файл

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
&colibri_gpio_keys {
status = "okay";
};
/* Colibri Ethernet */
&fec1 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog0>;
};
/* Colibri SPI */
&lpspi2 {
cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>,
<&lsio_gpio5 2 GPIO_ACTIVE_LOW>;
};
/* Colibri UART_B */
&lpuart0 {
status = "okay";
};
/* Colibri UART_C */
&lpuart2 {
status = "okay";
};
/* Colibri UART_A */
&lpuart3 {
status= "okay";
};
/* Colibri SDCard */
&usdhc2 {
status = "okay";
};

90
arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi Normal file
Просмотреть файл

@ -0,0 +1,90 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
#include <dt-bindings/input/linux-event-codes.h>
/ {
aliases {
rtc0 = &rtc_i2c;
rtc1 = &rtc;
};
/* fixed crystal dedicated to mcp25xx */
clk16m: clock-16mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
};
&colibri_gpio_keys {
status = "okay";
};
&i2c1 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/* Colibri SPI */
&lpspi2 {
status = "okay";
mcp2515: can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
interrupt-parent = <&lsio_gpio3>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_can_int>;
pinctrl-names = "default";
clocks = <&clk16m>;
spi-max-frequency = <10000000>;
};
};
/* Colibri UART_B */
&lpuart0 {
status = "okay";
};
/* Colibri UART_C */
&lpuart2 {
status = "okay";
};
/* Colibri PWM_B */
&lsio_pwm0 {
status = "okay";
};
/* Colibri PWM_C */
&lsio_pwm1 {
status = "okay";
};
/* Colibri PWM_D */
&lsio_pwm2 {
status = "okay";
};
/* Colibri UART_A */
&lpuart3 {
status = "okay";
};
/* Colibri FastEthernet */
&fec1 {
status = "okay";
};
/* Colibri SD/MMC Card */
&usdhc2 {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
#include "imx8x-colibri-iris.dtsi"
/ {
reg_3v3_vmmc: regulator-3v3-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
enable-active-high;
gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3v3_vmmc";
startup-delay-us = <100>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_converter &pinctrl_gpio_iris>;
pinctrl_enable_3v3_vmmc: enable_3v3_vmmc {
fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>; /* SODIMM 100 */
};
pinctrl_lvds_converter: lcd-lvds {
fsl,pins = <IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20>, /* SODIMM 55 */
/* 6B/8B mode. Select LOW - 8B mode (24bit) */
<IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20>, /* SODIMM 63 */
<IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
<IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>; /* SODIMM 99 */
};
};
/* Colibri SD/MMC Card */
&usdhc2 {
cap-power-off-card;
/delete-property/ no-1-8-v;
vmmc-supply = <&reg_3v3_vmmc>;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/ {
aliases {
rtc0 = &rtc_i2c;
rtc1 = &rtc;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V";
};
};
&colibri_gpio_keys {
status = "okay";
};
/* Colibri FastEthernet */
&fec1 {
status = "okay";
};
/* Colibri I2C */
&i2c1 {
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_iris>;
pinctrl_gpio_iris: gpioirisgrp {
fsl,pins = <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
<IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */
<IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
<IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
<IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
<IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
<IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
};
pinctrl_uart1_forceoff: uart1forceoffgrp {
fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>; /* SODIMM 22 */
};
pinctrl_uart23_forceoff: uart23forceoffgrp {
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>; /* SODIMM 23 */
};
};
/* Colibri SPI */
&lpspi2 {
status = "okay";
};
/* Colibri UART_B */
&lpuart0 {
status = "okay";
};
/* Colibri UART_C */
&lpuart2 {
status = "okay";
};
/* Colibri UART_A */
&lpuart3 {
status= "okay";
};
&lsio_gpio3 {
/*
* This turns the LVDS transceiver on. If one wants to turn the
* transceiver off, that property has to be deleted and the gpio handled
* in userspace.
*/
lvds-tx-on-hog {
gpio-hog;
gpios = <18 0>;
output-high;
};
};
/* Colibri PWM_B */
&lsio_pwm0 {
status = "okay";
};
/* Colibri PWM_C */
&lsio_pwm1 {
status = "okay";
};
/* Colibri PWM_D */
&lsio_pwm2 {
status = "okay";
};
/* Colibri SD/MMC Card */
&usdhc2 {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
/ {
chosen {
stdout-path = &lpuart3;
};
colibri_gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
status = "disabled";
key-wakeup {
debounce-interval = <10>;
gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
label = "Wake-Up";
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
/* TODO Analogue Inputs */
/* TODO Cooling maps for DX */
&cpu_alert0 {
hysteresis = <2000>;
temperature = <90000>;
type = "passive";
};
&cpu_crit0 {
hysteresis = <2000>;
temperature = <105000>;
type = "critical";
};
/* TODO flexcan1 - 3 */
/* TODO GPU */
/* On-module I2C */
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
status = "okay";
/* Touch controller */
touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ad7879_int>;
reg = <0x2c>;
interrupt-parent = <&lsio_gpio3>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
touchscreen-max-pressure = <4096>;
adi,resistance-plate-x = <120>;
adi,first-conversion-delay = /bits/ 8 <3>;
adi,acquisition-time = /bits/ 8 <1>;
adi,median-filter-size = /bits/ 8 <2>;
adi,averaging = /bits/ 8 <1>;
adi,conversion-interval = /bits/ 8 <255>;
status = "disabled";
};
};
/* TODO i2c lvds0 accessible on FFC (X2) */
/* TODO i2c lvds1 accessible on FFC (X3) */
/* Colibri I2C */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
};
&jpegdec {
status = "okay";
};
&jpegenc {
status = "okay";
};
/* TODO Parallel RRB */
/* Colibri UART_B */
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
};
/* Colibri UART_C */
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
};
/* Colibri UART_A */
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};
/* Colibri FastEthernet */
&fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
reg = <2>;
};
};
};
/* Colibri SPI */
&lpspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2>;
cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
};
&lsio_gpio0 {
gpio-line-names = "",
"SODIMM_70",
"SODIMM_60",
"SODIMM_58",
"SODIMM_78",
"SODIMM_72",
"SODIMM_80",
"SODIMM_46",
"SODIMM_62",
"SODIMM_48",
"SODIMM_74",
"SODIMM_50",
"SODIMM_52",
"SODIMM_54",
"SODIMM_66",
"SODIMM_64",
"SODIMM_68",
"",
"",
"SODIMM_82",
"SODIMM_56",
"SODIMM_28",
"SODIMM_30",
"",
"SODIMM_61",
"SODIMM_103",
"",
"",
"",
"SODIMM_25",
"SODIMM_27",
"SODIMM_100";
};
&lsio_gpio1 {
gpio-line-names = "SODIMM_86",
"SODIMM_92",
"SODIMM_90",
"SODIMM_88",
"",
"",
"",
"SODIMM_59",
"",
"SODIMM_6",
"SODIMM_8",
"",
"",
"SODIMM_2",
"SODIMM_4",
"SODIMM_34",
"SODIMM_32",
"SODIMM_63",
"SODIMM_55",
"SODIMM_33",
"SODIMM_35",
"SODIMM_36",
"SODIMM_38",
"SODIMM_21",
"SODIMM_19",
"SODIMM_140",
"SODIMM_142",
"SODIMM_196",
"SODIMM_194",
"SODIMM_186",
"SODIMM_188",
"SODIMM_138";
};
&lsio_gpio2 {
gpio-line-names = "SODIMM_23",
"",
"",
"SODIMM_144";
};
&lsio_gpio3 {
gpio-line-names = "SODIMM_96",
"SODIMM_75",
"SODIMM_37",
"SODIMM_29",
"",
"",
"",
"",
"",
"SODIMM_43",
"SODIMM_45",
"SODIMM_69",
"SODIMM_71",
"SODIMM_73",
"SODIMM_77",
"SODIMM_89",
"SODIMM_93",
"SODIMM_95",
"SODIMM_99",
"SODIMM_105",
"SODIMM_107",
"SODIMM_98",
"SODIMM_102",
"SODIMM_104",
"SODIMM_106";
};
&lsio_gpio4 {
gpio-line-names = "",
"",
"",
"SODIMM_129",
"SODIMM_133",
"SODIMM_127",
"SODIMM_131",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"SODIMM_44",
"",
"SODIMM_76",
"SODIMM_31",
"SODIMM_47",
"SODIMM_190",
"SODIMM_192",
"SODIMM_49",
"SODIMM_51",
"SODIMM_53";
};
&lsio_gpio5 {
gpio-line-names = "",
"SODIMM_57",
"SODIMM_65",
"SODIMM_85",
"",
"",
"",
"",
"SODIMM_135",
"SODIMM_137",
"UNUSABLE_SODIMM_180",
"UNUSABLE_SODIMM_184";
};
/* Colibri PWM_B */
&lsio_pwm0 {
#pwm-cells = <3>;
pinctrl-0 = <&pinctrl_pwm_b>;
pinctrl-names = "default";
};
/* Colibri PWM_C */
&lsio_pwm1 {
#pwm-cells = <3>;
pinctrl-0 = <&pinctrl_pwm_c>;
pinctrl-names = "default";
};
/* Colibri PWM_D */
&lsio_pwm2 {
#pwm-cells = <3>;
pinctrl-0 = <&pinctrl_pwm_d>;
pinctrl-names = "default";
};
/* TODO MIPI CSI */
/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */
/* TODO on-module PCIe for Wi-Fi */
/* TODO On-module i2s / Audio */
/* On-module eMMC */
&usdhc1 {
bus-width = <8>;
non-removable;
no-sd;
no-sdio;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
status = "okay";
};
/* Colibri SD/MMC Card */
&usdhc2 {
bus-width = <4>;
cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_module_3v3>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
disable-wp;
no-1-8-v;
};
/* TODO USB Client/Host */
/* TODO USB Host */
/* TODO VPU Encoder/Decoder */
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
<&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>;
/* On-module touch pen-down interrupt */
pinctrl_ad7879_int: ad7879intgrp {
fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>;
};
/* Colibri Analogue Inputs */
pinctrl_adc0: adc0grp {
fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60>, /* SODIMM 8 */
<IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60>, /* SODIMM 6 */
<IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60>, /* SODIMM 4 */
<IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60>; /* SODIMM 2 */
};
/* Atmel MXT touchsceen + Capacitive Touch Adapter */
/* NOTE: This pingroup conflicts with pingroups
* pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
* simultaneously.
*/
pinctrl_atmel_adap: atmeladaptergrp {
fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */
<IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */
};
/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
pinctrl_atmel_conn: atmelconnectorgrp {
fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */
<IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */
};
pinctrl_can_int: canintgrp {
fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40>; /* SODIMM 73 */
};
pinctrl_csi_ctl: csictlgrp {
fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>, /* SODIMM 77 */
<IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20>; /* SODIMM 89 */
};
pinctrl_csi_mclk: csimclkgrp {
fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */
};
pinctrl_ext_io0: extio0grp {
fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040>; /* SODIMM 135 */
};
/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
pinctrl_fec1: fec1grp {
fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
<IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
<IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61>,
<IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061>,
<IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61>,
<IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61>,
<IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61>,
<IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61>,
<IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61>,
<IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61>;
};
pinctrl_fec1_sleep: fec1slpgrp {
fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041>,
<IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041>,
<IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41>,
<IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41>,
<IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41>,
<IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41>,
<IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41>,
<IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41>,
<IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41>,
<IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41>;
};
/* Colibri optional CAN on UART_B RTS/CTS */
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21>, /* SODIMM 32 */
<IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21>; /* SODIMM 34 */
};
/* Colibri optional CAN on PS2 */
pinctrl_flexcan2: flexcan1grp {
fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21>, /* SODIMM 55 */
<IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21>; /* SODIMM 63 */
};
/* Colibri optional CAN on UART_A TXD/RXD */
pinctrl_flexcan3: flexcan2grp {
fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21>, /* SODIMM 35 */
<IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21>; /* SODIMM 33 */
};
/* Colibri LCD Back-Light GPIO */
pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60>; /* SODIMM 71 */
};
/* HDMI Hot Plug Detect on FFC (X2) */
pinctrl_gpio_hpd: gpiohpdgrp {
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20>; /* SODIMM 138 */
};
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
};
pinctrl_hog0: hog0grp {
fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */
<IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */
<IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
<IMX8QXP_CSI_D02_CI_PI_D04 0x61>, /* SODIMM 79 */
<IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
<IMX8QXP_CSI_D06_CI_PI_D08 0x61>, /* SODIMM 85 */
<IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
<IMX8QXP_CSI_D03_CI_PI_D05 0x61>, /* SODIMM 97 */
<IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */
<IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
<IMX8QXP_CSI_D00_CI_PI_D02 0x61>, /* SODIMM 101 */
<IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
<IMX8QXP_CSI_D01_CI_PI_D03 0x61>, /* SODIMM 103 */
<IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */
<IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20>, /* SODIMM 127 */
<IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20>, /* SODIMM 131 */
<IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */
<IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20>, /* SODIMM 96 */
<IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
<IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>, /* SODIMM 100 */
<IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20>, /* SODIMM 102 */
<IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20>; /* SODIMM 104 */
};
pinctrl_hog1: hog1grp {
fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>, /* SODIMM 75 */
<IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */
};
pinctrl_hog2: hog2grp {
fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>; /* SODIMM 75 */
};
/*
* This pin is used in the SCFW as a UART. Using it from
* Linux would require rewritting the SCFW board file.
*/
pinctrl_hog_scfw: hogscfwgrp {
fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */
};
/* On Module I2C */
pinctrl_i2c0: i2c0grp {
fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>,
<IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>;
};
/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020>, /* SODIMM 140 */
<IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020>; /* SODIMM 142 */
};
/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020>, /* SODIMM 186 */
<IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020>; /* SODIMM 188 */
};
/* Colibri I2C */
pinctrl_i2c1: i2c1grp {
fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021>, /* SODIMM 196 */
<IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021>; /* SODIMM 194 */
};
/* Colibri Parallel RGB LCD Interface */
pinctrl_lcdif: lcdifgrp {
fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60>, /* SODIMM 56 */
<IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60>, /* SODIMM 68 */
<IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60>, /* SODIMM 82 */
<IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40>, /* SODIMM 44 */
<IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40>, /* SODIMM 44 */
<IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60>, /* SODIMM 76 */
<IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60>, /* SODIMM 76 */
<IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60>, /* SODIMM 70 */
<IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60>, /* SODIMM 60 */
<IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60>, /* SODIMM 58 */
<IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60>, /* SODIMM 78 */
<IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60>, /* SODIMM 72 */
<IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60>, /* SODIMM 80 */
<IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60>, /* SODIMM 46 */
<IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60>, /* SODIMM 62 */
<IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60>, /* SODIMM 48 */
<IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60>, /* SODIMM 74 */
<IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60>, /* SODIMM 50 */
<IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60>, /* SODIMM 52 */
<IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60>, /* SODIMM 54 */
<IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60>, /* SODIMM 66 */
<IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60>, /* SODIMM 64 */
<IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60>, /* SODIMM 57 */
<IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60>, /* SODIMM 57 */
<IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60>; /* SODIMM 61 */
};
/* Colibri SPI */
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21>, /* SODIMM 86 */
<IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040>, /* SODIMM 92 */
<IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040>, /* SODIMM 90 */
<IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040>; /* SODIMM 88 */
};
pinctrl_lpspi2_cs2: lpspi2cs2grp {
fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21>; /* SODIMM 65 */
};
/* Colibri UART_B */
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, /* SODIMM 36 */
<IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>, /* SODIMM 38 */
<IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, /* SODIMM 34 */
<IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>; /* SODIMM 32 */
};
/* Colibri UART_C */
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020>, /* SODIMM 19 */
<IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020>; /* SODIMM 21 */
};
/* Colibri UART_A */
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, /* SODIMM 33 */
<IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; /* SODIMM 35 */
};
/* Colibri UART_A Control */
pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>, /* SODIMM 23 */
<IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20>, /* SODIMM 25 */
<IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20>, /* SODIMM 27 */
<IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20>, /* SODIMM 29 */
<IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20>, /* SODIMM 31 */
<IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20>; /* SODIMM 37 */
};
/* On module wifi module */
pinctrl_pcieb: pciebgrp {
fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061>, /* SODIMM 178 */
<IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061>, /* SODIMM 94 */
<IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60>; /* SODIMM 81 */
};
/* Colibri PWM_A */
pinctrl_pwm_a: pwmagrp {
/* both pins are connected together, reserve the unused CSI_D05 */
fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07 0x61>, /* SODIMM 59 */
<IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60>; /* SODIMM 59 */
};
/* Colibri PWM_B */
pinctrl_pwm_b: pwmbgrp {
fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60>; /* SODIMM 28 */
};
/* Colibri PWM_C */
pinctrl_pwm_c: pwmcgrp {
fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60>; /* SODIMM 30 */
};
/* Colibri PWM_D */
pinctrl_pwm_d: pwmdgrp {
/* both pins are connected together, reserve the unused CSI_D04 */
fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06 0x61>, /* SODIMM 67 */
<IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60>; /* SODIMM 67 */
};
/* On-module I2S */
pinctrl_sai0: sai0grp {
fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040>,
<IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040>,
<IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040>,
<IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040>;
};
/* Colibri Audio Analogue Microphone GND */
pinctrl_sgtl5000: sgtl5000grp {
fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41>;
};
/* On-module SGTL5000 clock */
pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21>;
};
/* On-module USB interrupt */
pinctrl_usb3503a: usb3503agrp {
fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61>;
};
/* Colibri USB Client Cable Detect */
pinctrl_usbc_det: usbcdetgrp {
fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040>; /* SODIMM 137 */
};
/* USB Host Power Enable */
pinctrl_usbh1_reg: usbh1reggrp {
fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040>; /* SODIMM 129 */
};
/* On-module eMMC */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
<IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
<IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
<IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
<IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
<IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
<IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
<IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
<IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
<IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
<IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
<IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
<IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
<IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
};
/* Colibri SD/MMC Card Detect */
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021>; /* SODIMM 43 */
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60>; /* SODIMM 43 */
};
/* Colibri SD/MMC Card */
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_usdhc2_sleep: usdhc2slpgrp {
fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60>, /* SODIMM 47 */
<IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60>, /* SODIMM 190 */
<IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60>, /* SODIMM 192 */
<IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60>, /* SODIMM 49 */
<IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60>, /* SODIMM 51 */
<IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60>, /* SODIMM 53 */
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>;
};
};

47
arch/arm64/boot/dts/freescale/imx93.dtsi
Просмотреть файл

@ -153,6 +153,14 @@
nxp,no-divider;
};
tpm1: pwm@44310000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x44310000 0x1000>;
clocks = <&clk IMX93_CLK_TPM1_GATE>;
#pwm-cells = <3>;
status = "disabled";
};
tpm2: pwm@44320000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x44320000 0x10000>;
@ -243,6 +251,22 @@
status = "okay";
};
bbnsm: bbnsm@44440000 {
compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
reg = <0x44440000 0x10000>;
bbnsm_rtc: rtc {
compatible = "nxp,imx93-bbnsm-rtc";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
bbnsm_pwrkey: pwrkey {
compatible = "nxp,imx93-bbnsm-pwrkey";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
linux,code = <KEY_POWER>;
};
};
clk: clock-controller@44450000 {
compatible = "fsl,imx93-ccm";
reg = <0x44450000 0x10000>;
@ -316,6 +340,14 @@
status = "disabled";
};
tpm3: pwm@424e0000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x424e0000 0x1000>;
clocks = <&clk IMX93_CLK_TPM3_GATE>;
#pwm-cells = <3>;
status = "disabled";
};
tpm4: pwm@424f0000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x424f0000 0x10000>;
@ -434,6 +466,21 @@
status = "disabled";
};
flexspi1: spi@425e0000 {
compatible = "nxp,imx8mm-fspi";
reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
<&clk IMX93_CLK_FLEXSPI1_GATE>;
clock-names = "fspi_en", "fspi";
assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
status = "disabled";
};
lpuart7: serial@42690000 {
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42690000 0x1000>;