omap: Add platform init code for EHCI driver
Add platform init code for EHCI driver. Various fixes to the original patch by Ajay Kumar Gupta <ajay.gupta@ti.com> and Anand Gadiyar <gadiyar@ti.com>. Overo support added by Olof Johansson <olof@lixom.net> Beagle support added by Koen Kooi <koen@beagleboard.org> CM-T32 support added by Mike Rapoport <mike@compulab.co.il> Signed-off-by: Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Koen Kooi <koen@beagleboard.org> Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Родитель
83720a8230
Коммит
58a5491c93
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@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
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# Platform specific device init code
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obj-y += usb-musb.o
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obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
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obj-y += usb-ehci.o
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onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
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obj-y += $(onenand-m) $(onenand-y)
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@ -494,6 +494,18 @@ static void enable_board_wakeup_source(void)
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omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
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}
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static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
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.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.phy_reset = true,
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.reset_gpio_port[0] = 57,
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.reset_gpio_port[1] = 61,
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.reset_gpio_port[2] = -EINVAL
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};
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static void __init omap_3430sdp_init(void)
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{
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omap3430_i2c_init();
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@ -510,6 +522,7 @@ static void __init omap_3430sdp_init(void)
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usb_musb_init();
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board_smc91x_init();
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enable_board_wakeup_source();
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usb_ehci_init(&ehci_pdata);
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}
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static void __init omap_3430sdp_map_io(void)
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@ -410,6 +410,18 @@ static void __init omap3beagle_flash_init(void)
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}
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}
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static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
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.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.phy_reset = true,
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.reset_gpio_port[0] = -EINVAL,
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.reset_gpio_port[1] = 147,
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.reset_gpio_port[2] = -EINVAL
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};
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static void __init omap3_beagle_init(void)
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{
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omap3_beagle_i2c_init();
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@ -423,6 +435,7 @@ static void __init omap3_beagle_init(void)
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gpio_direction_output(170, true);
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usb_musb_init();
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usb_ehci_init(&ehci_pdata);
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omap3beagle_flash_init();
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/* Ensure SDRC pins are mux'd for self-refresh */
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@ -307,6 +307,18 @@ static struct platform_device *omap3_evm_devices[] __initdata = {
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&omap3evm_smc911x_device,
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};
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static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
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.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.phy_reset = true,
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.reset_gpio_port[0] = -EINVAL,
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.reset_gpio_port[1] = 135,
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.reset_gpio_port[2] = -EINVAL
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};
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static void __init omap3_evm_init(void)
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{
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omap3_evm_i2c_init();
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@ -322,6 +334,9 @@ static void __init omap3_evm_init(void)
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usb_nop_xceiv_register();
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#endif
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usb_musb_init();
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/* Setup EHCI phy reset padconfig */
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omap_cfg_reg(AF4_34XX_GPIO135_OUT);
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usb_ehci_init(&ehci_pdata);
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ads7846_dev_init();
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}
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@ -397,6 +397,18 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
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&pandora_keys_gpio,
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};
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static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
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.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.phy_reset = true,
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.reset_gpio_port[0] = 16,
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.reset_gpio_port[1] = -EINVAL,
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.reset_gpio_port[2] = -EINVAL
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};
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static void __init omap3pandora_init(void)
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{
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omap3pandora_i2c_init();
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@ -406,6 +418,7 @@ static void __init omap3pandora_init(void)
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spi_register_board_info(omap3pandora_spi_board_info,
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ARRAY_SIZE(omap3pandora_spi_board_info));
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omap3pandora_ads7846_init();
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usb_ehci_init(&ehci_pdata);
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pandora_keys_gpio_init();
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usb_musb_init();
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@ -394,6 +394,18 @@ static struct platform_device *overo_devices[] __initdata = {
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&overo_lcd_device,
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};
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static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
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.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
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.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
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.phy_reset = true,
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.reset_gpio_port[0] = -EINVAL,
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.reset_gpio_port[1] = OVERO_GPIO_USBH_NRESET,
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.reset_gpio_port[2] = -EINVAL
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};
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static void __init overo_init(void)
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{
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overo_i2c_init();
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@ -401,6 +413,7 @@ static void __init overo_init(void)
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omap_serial_init();
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overo_flash_init();
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usb_musb_init();
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usb_ehci_init(&ehci_pdata);
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overo_ads7846_init();
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overo_init_smsc911x();
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@ -443,14 +456,6 @@ static void __init overo_init(void)
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else
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printk(KERN_ERR "could not obtain gpio for "
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"OVERO_GPIO_USBH_CPEN\n");
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if ((gpio_request(OVERO_GPIO_USBH_NRESET,
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"OVERO_GPIO_USBH_NRESET") == 0) &&
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(gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0))
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gpio_export(OVERO_GPIO_USBH_NRESET, 0);
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else
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printk(KERN_ERR "could not obtain gpio for "
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"OVERO_GPIO_USBH_NRESET\n");
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}
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static void __init overo_map_io(void)
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@ -0,0 +1,192 @@
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/*
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* linux/arch/arm/mach-omap2/usb-ehci.c
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*
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* This file will contain the board specific details for the
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* Synopsys EHCI host controller on OMAP3430
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*
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* Copyright (C) 2007 Texas Instruments
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* Author: Vikram Pandita <vikram.pandita@ti.com>
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*
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* Generalization by:
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* Felipe Balbi <felipe.balbi@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <plat/mux.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <plat/usb.h>
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#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
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static struct resource ehci_resources[] = {
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{
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.start = OMAP34XX_EHCI_BASE,
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.end = OMAP34XX_EHCI_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP34XX_UHH_CONFIG_BASE,
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.end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP34XX_USBTLL_BASE,
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.end = OMAP34XX_USBTLL_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{ /* general IRQ */
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.start = INT_34XX_EHCI_IRQ,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 ehci_dmamask = ~(u32)0;
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static struct platform_device ehci_device = {
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.name = "ehci-omap",
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.id = 0,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = NULL,
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},
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.num_resources = ARRAY_SIZE(ehci_resources),
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.resource = ehci_resources,
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};
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/* MUX settings for EHCI pins */
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/*
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* setup_ehci_io_mux - initialize IO pad mux for USBHOST
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*/
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static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
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{
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switch (port_mode[0]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
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omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
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omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
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omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
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omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
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omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
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omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
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omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
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omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
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omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
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omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
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omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
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omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
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omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
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omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
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omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
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omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
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omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
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omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
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omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
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omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
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omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
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omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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/* FALLTHROUGH */
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default:
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break;
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}
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switch (port_mode[1]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
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omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
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omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
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omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
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omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
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omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
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omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
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omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
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omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
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omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
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omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
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omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
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omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
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omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
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omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
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omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
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omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
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omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
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omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
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omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
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omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
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omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
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omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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/* FALLTHROUGH */
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default:
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break;
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}
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switch (port_mode[2]) {
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case EHCI_HCD_OMAP_MODE_PHY:
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printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
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break;
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case EHCI_HCD_OMAP_MODE_TLL:
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omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
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omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
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omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
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omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
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omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
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omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
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omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
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omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
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omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
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omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
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omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
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omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
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break;
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case EHCI_HCD_OMAP_MODE_UNKNOWN:
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/* FALLTHROUGH */
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default:
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break;
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}
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return;
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}
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void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
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{
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platform_device_add_data(&ehci_device, pdata, sizeof(*pdata));
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/* Setup Pin IO MUX for EHCI */
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if (cpu_is_omap34xx())
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setup_ehci_io_mux(pdata->port_mode);
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if (platform_device_register(&ehci_device) < 0) {
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printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
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return;
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}
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}
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#else
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void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
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{
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}
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#endif /* CONFIG_USB_EHCI_HCD */
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@ -74,8 +74,12 @@
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#define OMAP34XX_IVA_INTC_BASE 0x40000000
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#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
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#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
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#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
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#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
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#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
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#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
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#define OMAP34XX_SR1_BASE 0x480C9000
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#define OMAP34XX_SR2_BASE 0x480CB000
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#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
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