KVM: APIC: get rid of deliver_bitmask
Deliver interrupt during destination matching loop. Signed-off-by: Gleb Natapov <gleb@redhat.com> Acked-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
This commit is contained in:
Родитель
e1035715ef
Коммит
58c2dde17d
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@ -283,6 +283,18 @@ static int handle_sal_call(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
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}
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static int __apic_accept_irq(struct kvm_vcpu *vcpu, uint64_t vector)
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{
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struct vpd *vpd = to_host(vcpu->kvm, vcpu->arch.vpd);
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if (!test_and_set_bit(vector, &vpd->irr[0])) {
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vcpu->arch.irq_new_pending = 1;
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kvm_vcpu_kick(vcpu);
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return 1;
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}
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return 0;
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}
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/*
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* offset: address offset to IPI space.
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* value: deliver value.
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@ -292,20 +304,20 @@ static void vcpu_deliver_ipi(struct kvm_vcpu *vcpu, uint64_t dm,
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{
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switch (dm) {
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case SAPIC_FIXED:
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kvm_apic_set_irq(vcpu, vector, dm, 0);
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break;
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case SAPIC_NMI:
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kvm_apic_set_irq(vcpu, 2, dm, 0);
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vector = 2;
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break;
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case SAPIC_EXTINT:
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kvm_apic_set_irq(vcpu, 0, dm, 0);
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vector = 0;
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break;
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case SAPIC_INIT:
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case SAPIC_PMI:
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default:
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printk(KERN_ERR"kvm: Unimplemented Deliver reserved IPI!\n");
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break;
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return;
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}
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__apic_accept_irq(vcpu, vector);
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}
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static struct kvm_vcpu *lid_to_vcpu(struct kvm *kvm, unsigned long id,
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@ -1813,17 +1825,9 @@ void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
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put_cpu();
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}
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig)
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
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{
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struct vpd *vpd = to_host(vcpu->kvm, vcpu->arch.vpd);
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if (!test_and_set_bit(vec, &vpd->irr[0])) {
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vcpu->arch.irq_new_pending = 1;
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kvm_vcpu_kick(vcpu);
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return 1;
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}
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return 0;
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return __apic_accept_irq(vcpu, irq->vector);
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}
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int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
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@ -1844,6 +1848,7 @@ int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
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int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
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int short_hand, int dest, int dest_mode)
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{
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struct kvm_lapic *target = vcpu->arch.apic;
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return (dest_mode == 0) ?
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kvm_apic_match_physical_addr(target, dest) :
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kvm_apic_match_logical_addr(target, dest);
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@ -23,7 +23,7 @@ int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
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int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
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int short_hand, int dest, int dest_mode);
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int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
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bool kvm_apic_present(struct kvm_vcpu *vcpu);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
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#define kvm_apic_present(x) (true)
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#endif
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@ -199,27 +199,12 @@ EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
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static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
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int vector, int level, int trig_mode);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig)
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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int lapic_dmode;
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switch (dmode) {
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case IOAPIC_LOWEST_PRIORITY:
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lapic_dmode = APIC_DM_LOWEST;
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break;
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case IOAPIC_FIXED:
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lapic_dmode = APIC_DM_FIXED;
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break;
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case IOAPIC_NMI:
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lapic_dmode = APIC_DM_NMI;
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break;
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default:
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printk(KERN_DEBUG"Ignoring delivery mode %d\n", dmode);
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return 0;
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break;
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}
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return __apic_accept_irq(apic, lapic_dmode, vec, 1, trig);
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return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
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irq->level, irq->trig_mode);
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}
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static inline int apic_find_highest_isr(struct kvm_lapic *apic)
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@ -447,36 +432,24 @@ static void apic_send_ipi(struct kvm_lapic *apic)
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{
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u32 icr_low = apic_get_reg(apic, APIC_ICR);
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u32 icr_high = apic_get_reg(apic, APIC_ICR2);
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struct kvm_lapic_irq irq;
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unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
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unsigned int short_hand = icr_low & APIC_SHORT_MASK;
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unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
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unsigned int level = icr_low & APIC_INT_ASSERT;
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unsigned int dest_mode = icr_low & APIC_DEST_MASK;
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unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
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unsigned int vector = icr_low & APIC_VECTOR_MASK;
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DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
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int i;
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irq.vector = icr_low & APIC_VECTOR_MASK;
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irq.delivery_mode = icr_low & APIC_MODE_MASK;
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irq.dest_mode = icr_low & APIC_DEST_MASK;
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irq.level = icr_low & APIC_INT_ASSERT;
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irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
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irq.shorthand = icr_low & APIC_SHORT_MASK;
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irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
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apic_debug("icr_high 0x%x, icr_low 0x%x, "
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"short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
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"dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
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icr_high, icr_low, short_hand, dest,
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trig_mode, level, dest_mode, delivery_mode, vector);
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icr_high, icr_low, irq.shorthand, irq.dest,
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irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
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irq.vector);
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kvm_get_intr_delivery_bitmask(apic->vcpu->kvm, apic, dest, dest_mode,
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delivery_mode == APIC_DM_LOWEST, short_hand,
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deliver_bitmask);
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while ((i = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
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< KVM_MAX_VCPUS) {
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struct kvm_vcpu *vcpu = apic->vcpu->kvm->vcpus[i];
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__clear_bit(i, deliver_bitmask);
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if (vcpu)
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__apic_accept_irq(vcpu->arch.apic, delivery_mode,
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vector, level, trig_mode);
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}
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kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
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}
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static u32 apic_get_tmcct(struct kvm_lapic *apic)
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@ -31,14 +31,13 @@ u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
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int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
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int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 dmode, u8 trig);
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int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
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u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
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void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
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void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
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int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
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bool kvm_apic_present(struct kvm_vcpu *vcpu);
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bool kvm_lapic_present(struct kvm_vcpu *vcpu);
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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
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void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
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@ -57,4 +57,14 @@ union kvm_ioapic_redirect_entry {
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} fields;
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};
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struct kvm_lapic_irq {
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u32 vector;
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u32 delivery_mode;
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u32 dest_mode;
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u32 level;
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u32 trig_mode;
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u32 shorthand;
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u32 dest_id;
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};
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#endif /* __KVM_TYPES_H__ */
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@ -142,58 +142,33 @@ static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
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}
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}
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int ioapic_deliver_entry(struct kvm *kvm, union kvm_ioapic_redirect_entry *e)
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{
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DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
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int i, r = -1;
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kvm_get_intr_delivery_bitmask(kvm, NULL, e->fields.dest_id,
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e->fields.dest_mode,
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e->fields.delivery_mode == IOAPIC_LOWEST_PRIORITY,
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0, deliver_bitmask);
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if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
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ioapic_debug("no target on destination\n");
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return r;
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}
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while ((i = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
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< KVM_MAX_VCPUS) {
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struct kvm_vcpu *vcpu = kvm->vcpus[i];
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__clear_bit(i, deliver_bitmask);
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if (vcpu) {
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if (r < 0)
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r = 0;
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r += kvm_apic_set_irq(vcpu, e->fields.vector,
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e->fields.delivery_mode,
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e->fields.trig_mode);
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} else
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ioapic_debug("null destination vcpu: "
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"mask=%x vector=%x delivery_mode=%x\n",
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e->fields.deliver_bitmask,
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e->fields.vector, e->fields.delivery_mode);
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}
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return r;
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}
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static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
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{
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union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
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union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
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struct kvm_lapic_irq irqe;
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ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
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"vector=%x trig_mode=%x\n",
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entry.fields.dest, entry.fields.dest_mode,
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entry.fields.delivery_mode, entry.fields.vector,
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entry.fields.trig_mode);
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entry->fields.dest, entry->fields.dest_mode,
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entry->fields.delivery_mode, entry->fields.vector,
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entry->fields.trig_mode);
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irqe.dest_id = entry->fields.dest_id;
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irqe.vector = entry->fields.vector;
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irqe.dest_mode = entry->fields.dest_mode;
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irqe.trig_mode = entry->fields.trig_mode;
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irqe.delivery_mode = entry->fields.delivery_mode << 8;
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irqe.level = 1;
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irqe.shorthand = 0;
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#ifdef CONFIG_X86
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/* Always delivery PIT interrupt to vcpu 0 */
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if (irq == 0) {
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entry.fields.dest_mode = 0; /* Physical mode. */
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entry.fields.dest_id = ioapic->kvm->vcpus[0]->vcpu_id;
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irqe.dest_mode = 0; /* Physical mode. */
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irqe.dest_id = ioapic->kvm->vcpus[0]->vcpu_id;
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}
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#endif
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return ioapic_deliver_entry(ioapic->kvm, &entry);
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return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
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}
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
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@ -71,8 +71,6 @@ void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode);
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int kvm_ioapic_init(struct kvm *kvm);
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
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void kvm_ioapic_reset(struct kvm_ioapic *ioapic);
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void kvm_get_intr_delivery_bitmask(struct kvm *kvm, struct kvm_lapic *src,
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int dest_id, int dest_mode, bool low_prio, int short_hand,
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unsigned long *deliver_bitmask);
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int ioapic_deliver_entry(struct kvm *kvm, union kvm_ioapic_redirect_entry *e);
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int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
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struct kvm_lapic_irq *irq);
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#endif
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@ -22,6 +22,9 @@
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#include <linux/kvm_host.h>
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#include <asm/msidef.h>
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#ifdef CONFIG_IA64
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#include <asm/iosapic.h>
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#endif
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#include "irq.h"
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@ -43,61 +46,71 @@ static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
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return kvm_ioapic_set_irq(kvm->arch.vioapic, e->irqchip.pin, level);
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}
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void kvm_get_intr_delivery_bitmask(struct kvm *kvm, struct kvm_lapic *src,
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int dest_id, int dest_mode, bool low_prio, int short_hand,
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unsigned long *deliver_bitmask)
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inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
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{
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int i, lowest = -1;
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struct kvm_vcpu *vcpu;
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#ifdef CONFIG_IA64
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return irq->delivery_mode ==
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(IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
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#else
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return irq->delivery_mode == APIC_DM_LOWEST;
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#endif
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}
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if (dest_mode == 0 && dest_id == 0xff && low_prio)
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int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
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struct kvm_lapic_irq *irq)
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{
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int i, r = -1;
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struct kvm_vcpu *vcpu, *lowest = NULL;
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if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
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kvm_is_dm_lowest_prio(irq))
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printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
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bitmap_zero(deliver_bitmask, KVM_MAX_VCPUS);
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for (i = 0; i < KVM_MAX_VCPUS; i++) {
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vcpu = kvm->vcpus[i];
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if (!vcpu || !kvm_apic_present(vcpu))
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continue;
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if (!kvm_apic_match_dest(vcpu, src, short_hand, dest_id,
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dest_mode))
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if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
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irq->dest_id, irq->dest_mode))
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continue;
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if (!low_prio) {
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__set_bit(i, deliver_bitmask);
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if (!kvm_is_dm_lowest_prio(irq)) {
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if (r < 0)
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r = 0;
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r += kvm_apic_set_irq(vcpu, irq);
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} else {
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if (lowest < 0)
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lowest = i;
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if (kvm_apic_compare_prio(vcpu, kvm->vcpus[lowest]) < 0)
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lowest = i;
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if (!lowest)
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lowest = vcpu;
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else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
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lowest = vcpu;
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}
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}
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if (lowest != -1)
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__set_bit(lowest, deliver_bitmask);
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if (lowest)
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r = kvm_apic_set_irq(lowest, irq);
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return r;
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}
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static int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int level)
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{
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union kvm_ioapic_redirect_entry entry;
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struct kvm_lapic_irq irq;
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entry.bits = 0;
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entry.fields.dest_id = (e->msi.address_lo &
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irq.dest_id = (e->msi.address_lo &
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MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
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entry.fields.vector = (e->msi.data &
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irq.vector = (e->msi.data &
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MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
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entry.fields.dest_mode = test_bit(MSI_ADDR_DEST_MODE_SHIFT,
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(unsigned long *)&e->msi.address_lo);
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entry.fields.trig_mode = test_bit(MSI_DATA_TRIGGER_SHIFT,
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(unsigned long *)&e->msi.data);
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entry.fields.delivery_mode = test_bit(
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MSI_DATA_DELIVERY_MODE_SHIFT,
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(unsigned long *)&e->msi.data);
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irq.dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
|
||||
irq.trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
|
||||
irq.delivery_mode = e->msi.data & 0x700;
|
||||
irq.level = 1;
|
||||
irq.shorthand = 0;
|
||||
|
||||
/* TODO Deal with RH bit of MSI message address */
|
||||
return ioapic_deliver_entry(kvm, &entry);
|
||||
return kvm_irq_delivery_to_apic(kvm, NULL, &irq);
|
||||
}
|
||||
|
||||
/* This should be called with the kvm->lock mutex held
|
||||
|
|
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