irqchip/xilinx: Restructure and use jump label api
Add a global structure to house various variables. And cleanup read/write handling by using jump label api. Tested-by; Michal Simek <michal.simek@xilinx.com> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Zubair Lutfullah Kakakhel
Marc Zyngier
Родитель
a5734de263
Коммит
591db74bfa
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@ -14,10 +14,9 @@
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/jump_label.h>
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#include <linux/bug.h>
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static void __iomem *intc_baseaddr;
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/* No one else should require these constants, so define them locally here. */
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#define ISR 0x00 /* Interrupt Status Register */
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#define IPR 0x04 /* Interrupt Pending Register */
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@ -31,27 +30,30 @@ static void __iomem *intc_baseaddr;
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#define MER_ME (1<<0)
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#define MER_HIE (1<<1)
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static unsigned int (*read_fn)(void __iomem *);
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static void (*write_fn)(u32, void __iomem *);
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static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
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static void intc_write32(u32 val, void __iomem *addr)
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struct xintc_irq_chip {
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void __iomem *base;
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struct irq_domain *root_domain;
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u32 intr_mask;
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};
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static struct xintc_irq_chip *xintc_irqc;
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static void xintc_write(int reg, u32 data)
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{
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iowrite32(val, addr);
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if (static_branch_unlikely(&xintc_is_be))
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iowrite32be(data, xintc_irqc->base + reg);
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else
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iowrite32(data, xintc_irqc->base + reg);
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}
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static unsigned int intc_read32(void __iomem *addr)
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static unsigned int xintc_read(int reg)
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{
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return ioread32(addr);
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}
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static void intc_write32_be(u32 val, void __iomem *addr)
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{
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iowrite32be(val, addr);
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}
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static unsigned int intc_read32_be(void __iomem *addr)
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{
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return ioread32be(addr);
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if (static_branch_unlikely(&xintc_is_be))
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return ioread32be(xintc_irqc->base + reg);
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else
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return ioread32(xintc_irqc->base + reg);
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}
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static void intc_enable_or_unmask(struct irq_data *d)
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@ -65,21 +67,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
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* acks the irq before calling the interrupt handler
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*/
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if (irqd_is_level_type(d))
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write_fn(mask, intc_baseaddr + IAR);
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xintc_write(IAR, mask);
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write_fn(mask, intc_baseaddr + SIE);
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xintc_write(SIE, mask);
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}
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static void intc_disable_or_mask(struct irq_data *d)
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{
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pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
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write_fn(1 << d->hwirq, intc_baseaddr + CIE);
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xintc_write(CIE, 1 << d->hwirq);
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}
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static void intc_ack(struct irq_data *d)
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{
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pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
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write_fn(1 << d->hwirq, intc_baseaddr + IAR);
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xintc_write(IAR, 1 << d->hwirq);
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}
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static void intc_mask_ack(struct irq_data *d)
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@ -87,8 +89,8 @@ static void intc_mask_ack(struct irq_data *d)
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unsigned long mask = 1 << d->hwirq;
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pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
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write_fn(mask, intc_baseaddr + CIE);
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write_fn(mask, intc_baseaddr + IAR);
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xintc_write(CIE, mask);
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xintc_write(IAR, mask);
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}
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static struct irq_chip intc_dev = {
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@ -99,15 +101,13 @@ static struct irq_chip intc_dev = {
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.irq_mask_ack = intc_mask_ack,
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};
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static struct irq_domain *root_domain;
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unsigned int get_irq(void)
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{
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unsigned int hwirq, irq = -1;
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hwirq = read_fn(intc_baseaddr + IVR);
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hwirq = xintc_read(IVR);
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if (hwirq != -1U)
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irq = irq_find_mapping(root_domain, hwirq);
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irq = irq_find_mapping(xintc_irqc->root_domain, hwirq);
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pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
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@ -116,9 +116,7 @@ unsigned int get_irq(void)
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static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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u32 intr_mask = (u32)d->host_data;
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if (intr_mask & (1 << hw)) {
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if (xintc_irqc->intr_mask & (1 << hw)) {
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irq_set_chip_and_handler_name(irq, &intc_dev,
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handle_edge_irq, "edge");
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irq_clear_status_flags(irq, IRQ_LEVEL);
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@ -138,59 +136,75 @@ static const struct irq_domain_ops xintc_irq_domain_ops = {
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static int __init xilinx_intc_of_init(struct device_node *intc,
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struct device_node *parent)
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{
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u32 nr_irq, intr_mask;
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u32 nr_irq;
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int ret;
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struct xintc_irq_chip *irqc;
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intc_baseaddr = of_iomap(intc, 0);
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BUG_ON(!intc_baseaddr);
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if (xintc_irqc) {
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pr_err("irq-xilinx: Multiple instances aren't supported\n");
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return -EINVAL;
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}
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irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
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if (!irqc)
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return -ENOMEM;
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xintc_irqc = irqc;
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irqc->base = of_iomap(intc, 0);
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BUG_ON(!irqc->base);
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ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
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if (ret < 0) {
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pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
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return ret;
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goto err_alloc;
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}
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ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask);
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ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
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if (ret < 0) {
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pr_err("irq-xilinx: unable to read xlnx,kind-of-intr\n");
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return ret;
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goto err_alloc;
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}
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if (intr_mask >> nr_irq)
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if (irqc->intr_mask >> nr_irq)
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pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
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pr_info("irq-xilinx: %s: num_irq=%d, edge=0x%x\n",
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intc->full_name, nr_irq, intr_mask);
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intc->full_name, nr_irq, irqc->intr_mask);
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write_fn = intc_write32;
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read_fn = intc_read32;
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/*
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* Disable all external interrupts until they are
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* explicity requested.
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*/
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write_fn(0, intc_baseaddr + IER);
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xintc_write(IER, 0);
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/* Acknowledge any pending interrupts just in case. */
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write_fn(0xffffffff, intc_baseaddr + IAR);
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xintc_write(IAR, 0xffffffff);
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/* Turn on the Master Enable. */
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write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
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if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
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write_fn = intc_write32_be;
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read_fn = intc_read32_be;
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write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
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xintc_write(MER, MER_HIE | MER_ME);
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if (!(xintc_read(MER) & (MER_HIE | MER_ME))) {
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static_branch_enable(&xintc_is_be);
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xintc_write(MER, MER_HIE | MER_ME);
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}
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/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
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* lazy and Michal can clean it up to something nicer when he tests
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* and commits this patch. ~~gcl */
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root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
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(void *)intr_mask);
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irqc->root_domain = irq_domain_add_linear(intc, nr_irq,
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&xintc_irq_domain_ops, irqc);
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if (!irqc->root_domain) {
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pr_err("irq-xilinx: Unable to create IRQ domain\n");
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goto err_alloc;
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}
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irq_set_default_host(root_domain);
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irq_set_default_host(irqc->root_domain);
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return 0;
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err_alloc:
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xintc_irqc = NULL;
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kfree(irqc);
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return ret;
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}
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IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
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