dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
Split out the dt bindings for USB3 DP PHY from qcom,qmp bindings for modularity. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1589510358-3865-3-git-send-email-sanm@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sandeep Maheswaram
Vinod Koul
Родитель
ccf51c1ced
Коммит
59351049ad
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@ -27,21 +27,13 @@ properties:
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- qcom,sdm845-qhp-pcie-phy
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- qcom,sdm845-qmp-pcie-phy
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- qcom,sdm845-qmp-ufs-phy
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- qcom,sdm845-qmp-usb3-phy
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- qcom,sdm845-qmp-usb3-uni-phy
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- qcom,sm8150-qmp-ufs-phy
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- qcom,sm8250-qmp-ufs-phy
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reg:
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minItems: 1
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items:
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- description: Address and length of PHY's common serdes block.
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- description: Address and length of the DP_COM control block.
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reg-names:
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items:
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- const: reg-base
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- const: dp_com
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"#clock-cells":
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enum: [ 1, 2 ]
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@ -110,7 +102,6 @@ allOf:
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compatible:
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contains:
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enum:
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- qcom,sdm845-qmp-usb3-phy
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- qcom,sdm845-qmp-usb3-uni-phy
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then:
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properties:
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@ -284,51 +275,39 @@ allOf:
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reset-names:
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items:
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- const: phy
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- if:
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properties:
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compatible:
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contains:
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const: qcom,sdm845-qmp-usb3-phy
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then:
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required:
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- reg-names
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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usb_1_qmpphy: phy-wrapper@88e9000 {
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compatible = "qcom,sdm845-qmp-usb3-phy";
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reg = <0 0x088e9000 0 0x18c>,
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<0 0x088e8000 0 0x10>;
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reg-names = "reg-base", "dp_com";
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usb_2_qmpphy: phy-wrapper@88eb000 {
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compatible = "qcom,sdm845-qmp-usb3-uni-phy";
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reg = <0 0x088eb000 0 0x18c>;
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#clock-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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<&gcc GCC_USB3_SEC_CLKREF_CLK>,
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<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "com_aux";
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resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
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resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
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<&gcc GCC_USB3_PHY_SEC_BCR>;
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reset-names = "phy", "common";
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vdda-phy-supply = <&vdda_usb2_ss_1p2>;
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vdda-pll-supply = <&vdda_usb2_ss_core>;
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usb_1_ssphy: phy@88e9200 {
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reg = <0 0x088e9200 0 0x128>,
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<0 0x088e9400 0 0x200>,
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<0 0x088e9c00 0 0x218>,
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<0 0x088e9600 0 0x128>,
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<0 0x088e9800 0 0x200>,
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<0 0x088e9a00 0 0x100>;
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usb_2_ssphy: phy@88eb200 {
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reg = <0 0x088eb200 0 0x128>,
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<0 0x088eb400 0 0x1fc>,
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<0 0x088eb800 0 0x218>,
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<0 0x088eb600 0 0x70>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_phy_pipe_clk_src";
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clock-output-names = "usb3_uni_phy_pipe_clk_src";
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};
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};
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@ -0,0 +1,135 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm QMP USB3 DP PHY controller
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maintainers:
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- Manu Gautam <mgautam@codeaurora.org>
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properties:
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compatible:
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const:
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qcom,sdm845-qmp-usb3-phy
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reg:
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items:
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- description: Address and length of PHY's common serdes block.
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- description: Address and length of the DP_COM control block.
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reg-names:
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items:
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- const: reg-base
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- const: dp_com
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"#clock-cells":
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enum: [ 1, 2 ]
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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clocks:
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items:
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- description: Phy aux clock.
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- description: Phy config clock.
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- description: 19.2 MHz ref clk.
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- description: Phy common block aux clock.
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clock-names:
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items:
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- const: aux
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- const: cfg_ahb
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- const: ref
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- const: com_aux
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resets:
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items:
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- description: reset of phy block.
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- description: phy common block reset.
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reset-names:
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items:
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- const: phy
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- const: common
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vdda-phy-supply:
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description:
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Phandle to a regulator supply to PHY core block.
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vdda-pll-supply:
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description:
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Phandle to 1.8V regulator supply to PHY refclk pll block.
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vddp-ref-clk-supply:
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description:
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Phandle to a regulator supply to any specific refclk
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pll block.
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#Required nodes:
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patternProperties:
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"^phy@[0-9a-f]+$":
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type: object
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description:
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Each device node of QMP phy is required to have as many child nodes as
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the number of lanes the PHY has.
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required:
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- compatible
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- reg
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- reg-names
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- "#clock-cells"
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- "#address-cells"
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- "#size-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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- vdda-phy-supply
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- vdda-pll-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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usb_1_qmpphy: phy-wrapper@88e9000 {
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compatible = "qcom,sdm845-qmp-usb3-phy";
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reg = <0 0x088e9000 0 0x18c>,
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<0 0x088e8000 0 0x10>;
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reg-names = "reg-base", "dp_com";
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#clock-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux", "cfg_ahb", "ref", "com_aux";
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resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
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reset-names = "phy", "common";
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vdda-phy-supply = <&vdda_usb2_ss_1p2>;
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vdda-pll-supply = <&vdda_usb2_ss_core>;
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usb_1_ssphy: phy@88e9200 {
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reg = <0 0x088e9200 0 0x128>,
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<0 0x088e9400 0 0x200>,
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<0 0x088e9c00 0 0x218>,
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<0 0x088e9600 0 0x128>,
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<0 0x088e9800 0 0x200>,
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<0 0x088e9a00 0 0x100>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_phy_pipe_clk_src";
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};
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};
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