[SCSI] isci: oem parameter format v1.1 (ssc select)
v1.1 allows finer grained tuning of the SSC (spread-spectrum-clocking) settings for SAS and SATA. See notes in probe_roms.h Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Dave Jiang
James Bottomley
Родитель
afd13a1f2b
Коммит
594e566ae5
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@ -1759,7 +1759,7 @@ static enum sci_status sci_controller_construct(struct isci_host *ihost,
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return sci_controller_reset(ihost);
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}
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int sci_oem_parameters_validate(struct sci_oem_params *oem)
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int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
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{
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int i;
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@ -1791,18 +1791,61 @@ int sci_oem_parameters_validate(struct sci_oem_params *oem)
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oem->controller.max_concurr_spin_up < 1)
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return -EINVAL;
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if (oem->controller.do_enable_ssc) {
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if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
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return -EINVAL;
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if (version >= ISCI_ROM_VER_1_1) {
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u8 test = oem->controller.ssc_sata_tx_spread_level;
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switch (test) {
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case 0:
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case 2:
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case 3:
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case 6:
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case 7:
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break;
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default:
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return -EINVAL;
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}
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test = oem->controller.ssc_sas_tx_spread_level;
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if (oem->controller.ssc_sas_tx_type == 0) {
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switch (test) {
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case 0:
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case 2:
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case 3:
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break;
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default:
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return -EINVAL;
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}
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} else if (oem->controller.ssc_sas_tx_type == 1) {
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switch (test) {
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case 0:
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case 3:
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case 6:
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break;
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default:
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return -EINVAL;
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}
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}
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}
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}
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return 0;
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}
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static enum sci_status sci_oem_parameters_set(struct isci_host *ihost)
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{
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u32 state = ihost->sm.current_state_id;
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struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
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if (state == SCIC_RESET ||
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state == SCIC_INITIALIZING ||
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state == SCIC_INITIALIZED) {
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if (sci_oem_parameters_validate(&ihost->oem_parameters))
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if (sci_oem_parameters_validate(&ihost->oem_parameters,
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pci_info->orom->hdr.version))
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return SCI_FAILURE_INVALID_PARAMETER_VALUE;
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return SCI_SUCCESS;
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@ -466,7 +466,8 @@ static int __devinit isci_pci_probe(struct pci_dev *pdev, const struct pci_devic
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orom = isci_request_oprom(pdev);
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for (i = 0; orom && i < ARRAY_SIZE(orom->ctrl); i++) {
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if (sci_oem_parameters_validate(&orom->ctrl[i])) {
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if (sci_oem_parameters_validate(&orom->ctrl[i],
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orom->hdr.version)) {
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dev_warn(&pdev->dev,
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"[%d]: invalid oem parameters detected, falling back to firmware\n", i);
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devm_kfree(&pdev->dev, orom);
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@ -144,10 +144,59 @@ sci_phy_link_layer_initialization(struct isci_phy *iphy,
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phy_cap.gen3_no_ssc = 1;
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phy_cap.gen2_no_ssc = 1;
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phy_cap.gen1_no_ssc = 1;
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if (ihost->oem_parameters.controller.do_enable_ssc == true) {
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if (ihost->oem_parameters.controller.do_enable_ssc) {
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struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
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struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_idx];
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struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
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bool en_sas = false;
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bool en_sata = false;
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u32 sas_type = 0;
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u32 sata_spread = 0x2;
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u32 sas_spread = 0x2;
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phy_cap.gen3_ssc = 1;
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phy_cap.gen2_ssc = 1;
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phy_cap.gen1_ssc = 1;
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if (pci_info->orom->hdr.version < ISCI_ROM_VER_1_1)
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en_sas = en_sata = true;
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else {
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sata_spread = ihost->oem_parameters.controller.ssc_sata_tx_spread_level;
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sas_spread = ihost->oem_parameters.controller.ssc_sas_tx_spread_level;
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if (sata_spread)
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en_sata = true;
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if (sas_spread) {
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en_sas = true;
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sas_type = ihost->oem_parameters.controller.ssc_sas_tx_type;
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}
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}
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if (en_sas) {
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u32 reg;
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reg = readl(&xcvr->afe_xcvr_control0);
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reg |= (0x00100000 | (sas_type << 19));
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writel(reg, &xcvr->afe_xcvr_control0);
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reg = readl(&xcvr->afe_tx_ssc_control);
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reg |= sas_spread << 8;
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writel(reg, &xcvr->afe_tx_ssc_control);
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}
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if (en_sata) {
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u32 reg;
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reg = readl(&xcvr->afe_tx_ssc_control);
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reg |= sata_spread;
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writel(reg, &xcvr->afe_tx_ssc_control);
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reg = readl(&llr->stp_control);
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reg |= 1 << 12;
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writel(reg, &llr->stp_control);
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}
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}
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/* The SAS specification indicates that the phy_capabilities that
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@ -152,7 +152,7 @@ struct sci_user_parameters {
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#define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4
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struct sci_oem_params;
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int sci_oem_parameters_validate(struct sci_oem_params *oem);
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int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version);
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struct isci_orom;
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struct isci_orom *isci_request_oprom(struct pci_dev *pdev);
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@ -191,6 +191,10 @@ struct isci_oem_hdr {
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0x1a, 0x04, 0xc6)
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#define ISCI_EFI_VAR_NAME "RstScuO"
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#define ISCI_ROM_VER_1_0 0x10
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#define ISCI_ROM_VER_1_1 0x11
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#define ISCI_ROM_VER_LATEST ISCI_ROM_VER_1_1
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/* Allowed PORT configuration modes APC Automatic PORT configuration mode is
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* defined by the OEM configuration parameters providing no PHY_MASK parameters
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* for any PORT. i.e. There are no phys assigned to any of the ports at start.
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@ -220,7 +224,52 @@ struct sci_oem_params {
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struct {
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uint8_t mode_type;
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uint8_t max_concurr_spin_up;
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uint8_t do_enable_ssc;
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/*
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* This bitfield indicates the OEM's desired default Tx
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* Spread Spectrum Clocking (SSC) settings for SATA and SAS.
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* NOTE: Default SSC Modulation Frequency is 31.5KHz.
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*/
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union {
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struct {
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/*
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* NOTE: Max spread for SATA is +0 / -5000 PPM.
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* Down-spreading SSC (only method allowed for SATA):
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* SATA SSC Tx Disabled = 0x0
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* SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
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* SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
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* SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
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* SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
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*/
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uint8_t ssc_sata_tx_spread_level:4;
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/*
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* SAS SSC Tx Disabled = 0x0
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*
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* NOTE: Max spread for SAS down-spreading +0 /
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* -2300 PPM
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* Down-spreading SSC:
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* SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
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* SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
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*
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* NOTE: Max spread for SAS center-spreading +2300 /
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* -2300 PPM
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* Center-spreading SSC:
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* SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
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* SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
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*/
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uint8_t ssc_sas_tx_spread_level:3;
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/*
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* NOTE: Refer to the SSC section of the SAS 2.x
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* Specification for proper setting of this field.
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* For standard SAS Initiator SAS PHY operation it
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* should be 0 for Down-spreading.
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* SAS SSC Tx spread type:
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* Down-spreading SSC = 0
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* Center-spreading SSC = 1
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*/
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uint8_t ssc_sas_tx_type:1;
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};
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uint8_t do_enable_ssc;
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};
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uint8_t reserved;
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} controller;
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