drm/radeon/si: properly set up the clearstate buffer for pg (v2)
The format of the clearstate buffer used for pg (powergating) changed between NI and SI. This formats it properly for what the hardware expects on SI. v2: fix addresses Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
Родитель
090f4b6ad3
Коммит
59a82d0e65
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@ -142,6 +142,9 @@ extern void cayman_vm_decode_fault(struct radeon_device *rdev,
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u32 status, u32 addr);
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void cik_init_cp_pg_table(struct radeon_device *rdev);
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extern u32 si_get_csb_size(struct radeon_device *rdev);
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extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
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static const u32 evergreen_golden_registers[] =
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{
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0x3f90, 0xffff0000, 0xff000000,
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@ -3893,7 +3896,7 @@ int sumo_rlc_init(struct radeon_device *rdev)
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const u32 *src_ptr;
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volatile u32 *dst_ptr;
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u32 dws, data, i, j, k, reg_num;
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u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index;
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u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index = 0;
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u64 reg_list_mc_addr;
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const struct cs_section_def *cs_data;
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int r;
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@ -3937,7 +3940,7 @@ int sumo_rlc_init(struct radeon_device *rdev)
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dst_ptr = rdev->rlc.sr_ptr;
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if (rdev->family >= CHIP_TAHITI) {
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/* SI */
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for (i = 0; i < dws; i++)
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for (i = 0; i < rdev->rlc.reg_list_size; i++)
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dst_ptr[i] = src_ptr[i];
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} else {
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/* ON/LN/TN */
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@ -3963,20 +3966,25 @@ int sumo_rlc_init(struct radeon_device *rdev)
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if (cs_data) {
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/* clear state block */
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reg_list_num = 0;
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dws = 0;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_list_num++;
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dws += cs_data[i].section[j].reg_count;
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if (rdev->family >= CHIP_TAHITI) {
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rdev->rlc.clear_state_size = si_get_csb_size(rdev);
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dws = rdev->rlc.clear_state_size + (256 / 4);
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} else {
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reg_list_num = 0;
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dws = 0;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_list_num++;
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dws += cs_data[i].section[j].reg_count;
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}
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}
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reg_list_blk_index = (3 * reg_list_num + 2);
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dws += reg_list_blk_index;
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rdev->rlc.clear_state_size = dws;
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}
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reg_list_blk_index = (3 * reg_list_num + 2);
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dws += reg_list_blk_index;
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rdev->rlc.clear_state_size = dws;
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if (rdev->rlc.clear_state_obj == NULL) {
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r = radeon_bo_create(rdev, rdev->rlc.clear_state_size * 4, PAGE_SIZE, true,
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r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
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@ -4006,36 +4014,43 @@ int sumo_rlc_init(struct radeon_device *rdev)
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}
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/* set up the cs buffer */
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dst_ptr = rdev->rlc.cs_ptr;
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reg_list_hdr_blk_index = 0;
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reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
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data = upper_32_bits(reg_list_mc_addr);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_num = cs_data[i].section[j].reg_count;
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data = reg_list_mc_addr & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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if (rdev->family >= CHIP_TAHITI) {
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reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
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dst_ptr[0] = upper_32_bits(reg_list_mc_addr);
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dst_ptr[1] = lower_32_bits(reg_list_mc_addr);
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dst_ptr[2] = rdev->rlc.clear_state_size;
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si_get_csb_buffer(rdev, &dst_ptr[(256/4)]);
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} else {
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reg_list_hdr_blk_index = 0;
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reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
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data = upper_32_bits(reg_list_mc_addr);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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for (i = 0; cs_data[i].section != NULL; i++) {
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for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
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reg_num = cs_data[i].section[j].reg_count;
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data = reg_list_mc_addr & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = 0x08000000 | (reg_num * 4);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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data = 0x08000000 | (reg_num * 4);
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dst_ptr[reg_list_hdr_blk_index] = data;
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reg_list_hdr_blk_index++;
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for (k = 0; k < reg_num; k++) {
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data = cs_data[i].section[j].extent[k];
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dst_ptr[reg_list_blk_index + k] = data;
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for (k = 0; k < reg_num; k++) {
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data = cs_data[i].section[j].extent[k];
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dst_ptr[reg_list_blk_index + k] = data;
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}
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reg_list_mc_addr += reg_num * 4;
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reg_list_blk_index += reg_num;
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}
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reg_list_mc_addr += reg_num * 4;
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reg_list_blk_index += reg_num;
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}
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dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
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}
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dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
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radeon_bo_kunmap(rdev->rlc.clear_state_obj);
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radeon_bo_unreserve(rdev->rlc.clear_state_obj);
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}
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@ -5286,6 +5286,97 @@ void si_update_pg(struct radeon_device *rdev,
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si_enable_gfx_cgpg(rdev, enable);
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}
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u32 si_get_csb_size(struct radeon_device *rdev)
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{
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u32 count = 0;
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const struct cs_section_def *sect = NULL;
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const struct cs_extent_def *ext = NULL;
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if (rdev->rlc.cs_data == NULL)
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return 0;
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/* begin clear state */
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count += 2;
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/* context control state */
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count += 3;
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for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
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for (ext = sect->section; ext->extent != NULL; ++ext) {
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if (sect->id == SECT_CONTEXT)
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count += 2 + ext->reg_count;
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else
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return 0;
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}
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}
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/* pa_sc_raster_config */
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count += 3;
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/* end clear state */
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count += 2;
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/* clear state */
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count += 2;
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return count;
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}
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void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
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{
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u32 count = 0, i;
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const struct cs_section_def *sect = NULL;
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const struct cs_extent_def *ext = NULL;
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if (rdev->rlc.cs_data == NULL)
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return;
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if (buffer == NULL)
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return;
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buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);
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buffer[count++] = PACKET3_PREAMBLE_BEGIN_CLEAR_STATE;
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buffer[count++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1);
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buffer[count++] = 0x80000000;
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buffer[count++] = 0x80000000;
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for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
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for (ext = sect->section; ext->extent != NULL; ++ext) {
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if (sect->id == SECT_CONTEXT) {
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buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count);
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buffer[count++] = ext->reg_index - 0xa000;
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for (i = 0; i < ext->reg_count; i++)
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buffer[count++] = ext->extent[i];
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} else {
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return;
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}
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}
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}
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buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
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buffer[count++] = PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START;
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switch (rdev->family) {
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case CHIP_TAHITI:
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case CHIP_PITCAIRN:
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buffer[count++] = 0x2a00126a;
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break;
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case CHIP_VERDE:
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buffer[count++] = 0x0000124a;
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break;
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case CHIP_OLAND:
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buffer[count++] = 0x00000082;
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break;
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case CHIP_HAINAN:
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buffer[count++] = 0x00000000;
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break;
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default:
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buffer[count++] = 0x00000000;
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break;
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}
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buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);
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buffer[count++] = PACKET3_PREAMBLE_END_CLEAR_STATE;
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buffer[count++] = PACKET3(PACKET3_CLEAR_STATE, 0);
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buffer[count++] = 0;
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}
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static void si_init_pg(struct radeon_device *rdev)
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{
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if (rdev->pg_flags) {
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