drm/i915: Clean up DP pipe select bits
Clean up the DP pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state(),
the port state asserts, and the VLV power sequencer code.
v2: Return PIPE_A for cpt/ppt when the port isn't selected by
any transcoder. Returning INVALID_PIPE explodes *somewhere*
on some machines (can't immediately see where though). This
now matches the old behaviour.
v3: Order the defines shift,mask,value (Jani)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
Родитель
5a0b385e1c
Коммит
59b74c497a
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@ -5182,10 +5182,15 @@ enum {
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#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
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#define DP_PORT_EN (1 << 31)
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#define DP_PIPEB_SELECT (1 << 30)
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#define DP_PIPE_MASK (1 << 30)
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#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
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#define DP_PIPE_MASK_CHV (3 << 16)
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#define DP_PIPE_SEL_SHIFT 30
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#define DP_PIPE_SEL_MASK (1 << 30)
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#define DP_PIPE_SEL(pipe) ((pipe) << 30)
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#define DP_PIPE_SEL_SHIFT_IVB 29
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#define DP_PIPE_SEL_MASK_IVB (3 << 29)
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#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
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#define DP_PIPE_SEL_SHIFT_CHV 16
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#define DP_PIPE_SEL_MASK_CHV (3 << 16)
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#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
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/* Link training mode - select a suitable mode for each stage */
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#define DP_LINK_TRAIN_PAT_1 (0 << 28)
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@ -7872,16 +7877,6 @@ enum {
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#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
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/* CPT */
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#define PORT_TRANS_A_SEL_CPT 0
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#define PORT_TRANS_B_SEL_CPT (1<<29)
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#define PORT_TRANS_C_SEL_CPT (2<<29)
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#define PORT_TRANS_SEL_MASK (3<<29)
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#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
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#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
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#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
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#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
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#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
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#define _TRANS_DP_CTL_A 0xe0300
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#define _TRANS_DP_CTL_B 0xe1300
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#define _TRANS_DP_CTL_C 0xe2300
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@ -7890,7 +7885,6 @@ enum {
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#define TRANS_DP_PORT_SEL_MASK (3 << 29)
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#define TRANS_DP_PORT_SEL_NONE (3 << 29)
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#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
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#define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
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#define TRANS_DP_AUDIO_ONLY (1<<26)
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#define TRANS_DP_ENH_FRAMING (1<<18)
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#define TRANS_DP_8BPC (0<<9)
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@ -1303,38 +1303,22 @@ void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
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pipe_name(pipe));
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}
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static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
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enum pipe pipe, u32 port_sel, u32 val)
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{
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if ((val & DP_PORT_EN) == 0)
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return false;
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if (HAS_PCH_CPT(dev_priv)) {
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u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
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if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
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return false;
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} else if (IS_CHERRYVIEW(dev_priv)) {
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if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
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return false;
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} else {
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if ((val & DP_PIPE_MASK) != (pipe << 30))
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return false;
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}
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return true;
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}
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static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe, i915_reg_t reg,
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u32 port_sel)
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enum pipe pipe, enum port port,
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i915_reg_t dp_reg)
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{
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u32 val = I915_READ(reg);
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I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
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"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
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i915_mmio_reg_offset(reg), pipe_name(pipe));
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enum pipe port_pipe;
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bool state;
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I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
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&& (val & DP_PIPEB_SELECT),
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"IBX PCH dp port still using transcoder B\n");
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state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
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I915_STATE_WARN(state && port_pipe == pipe,
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"PCH DP %c enabled on transcoder %c, should be disabled\n",
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port_name(port), pipe_name(pipe));
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I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
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"IBX PCH DP %c still using transcoder B\n",
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port_name(port));
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}
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static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
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@ -1360,9 +1344,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
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{
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enum pipe port_pipe;
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL(PORT_B));
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL(PORT_C));
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assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL(PORT_D));
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assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
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assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
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assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
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I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
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port_pipe == pipe,
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@ -529,9 +529,9 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
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DP |= DP_LINK_TRAIN_PAT_1;
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if (IS_CHERRYVIEW(dev_priv))
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DP |= DP_PIPE_SELECT_CHV(pipe);
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else if (pipe == PIPE_B)
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DP |= DP_PIPEB_SELECT;
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DP |= DP_PIPE_SEL_CHV(pipe);
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else
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DP |= DP_PIPE_SEL(pipe);
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pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
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@ -1974,7 +1974,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
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if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
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intel_dp->DP |= DP_ENHANCED_FRAMING;
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intel_dp->DP |= crtc->pipe << 29;
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intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
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} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
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u32 trans_dp;
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@ -2000,9 +2000,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
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intel_dp->DP |= DP_ENHANCED_FRAMING;
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if (IS_CHERRYVIEW(dev_priv))
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intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
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else if (crtc->pipe == PIPE_B)
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intel_dp->DP |= DP_PIPEB_SELECT;
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intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
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else
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intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
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}
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}
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@ -2624,52 +2624,66 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
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mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
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}
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static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
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enum port port, enum pipe *pipe)
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{
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enum pipe p;
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for_each_pipe(dev_priv, p) {
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u32 val = I915_READ(TRANS_DP_CTL(p));
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if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
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*pipe = p;
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return true;
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}
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}
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DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
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/* must initialize pipe to something for the asserts */
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*pipe = PIPE_A;
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return false;
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}
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bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
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i915_reg_t dp_reg, enum port port,
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enum pipe *pipe)
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{
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bool ret;
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u32 val;
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val = I915_READ(dp_reg);
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ret = val & DP_PORT_EN;
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/* asserts want to know the pipe even if the port is disabled */
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if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
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*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
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else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
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ret &= cpt_dp_port_selected(dev_priv, port, pipe);
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else if (IS_CHERRYVIEW(dev_priv))
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*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
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else
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*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
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return ret;
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}
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static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
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enum pipe *pipe)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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enum port port = encoder->port;
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u32 tmp;
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bool ret;
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if (!intel_display_power_get_if_enabled(dev_priv,
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encoder->power_domain))
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return false;
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ret = false;
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ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
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encoder->port, pipe);
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tmp = I915_READ(intel_dp->output_reg);
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if (!(tmp & DP_PORT_EN))
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goto out;
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if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
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*pipe = PORT_TO_PIPE_CPT(tmp);
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} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
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enum pipe p;
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for_each_pipe(dev_priv, p) {
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u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
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if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
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*pipe = p;
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ret = true;
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goto out;
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}
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}
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DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
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i915_mmio_reg_offset(intel_dp->output_reg));
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} else if (IS_CHERRYVIEW(dev_priv)) {
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*pipe = DP_PORT_TO_PIPE_CHV(tmp);
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} else {
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*pipe = PORT_TO_PIPE(tmp);
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}
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ret = true;
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out:
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intel_display_power_put(dev_priv, encoder->power_domain);
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return ret;
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@ -3659,8 +3673,9 @@ intel_dp_link_down(struct intel_encoder *encoder,
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intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
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/* always enable with pattern 1 (as per spec) */
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DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
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DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
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DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
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DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
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DP_LINK_TRAIN_PAT_1;
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I915_WRITE(intel_dp->output_reg, DP);
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POSTING_READ(intel_dp->output_reg);
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@ -5295,14 +5310,14 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
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static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
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struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
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enum pipe pipe;
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if ((intel_dp->DP & DP_PORT_EN) == 0)
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return INVALID_PIPE;
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if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
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encoder->port, &pipe))
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return pipe;
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if (IS_CHERRYVIEW(dev_priv))
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return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
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else
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return PORT_TO_PIPE(intel_dp->DP);
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return INVALID_PIPE;
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}
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void intel_dp_encoder_reset(struct drm_encoder *encoder)
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@ -1645,6 +1645,9 @@ void intel_csr_ucode_suspend(struct drm_i915_private *);
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void intel_csr_ucode_resume(struct drm_i915_private *);
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/* intel_dp.c */
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bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
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i915_reg_t dp_reg, enum port port,
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enum pipe *pipe);
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bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
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enum port port);
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bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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