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sh: Kill off dead boards. 

None of these have been maintained in years, and no one seems to
be interested in doing so, so just get rid of them.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2006-09-27 18:00:19 +09:00
Родитель f118420be8
Коммит 5a4053b232
43 изменённых файлов: 4 добавлений и 2892 удалений
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43
arch/sh/Kconfig
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@ -89,12 +89,6 @@ config SH_7751_SYSTEMH
Select SystemH if you are configuring for a Renesas SystemH
7751R evaluation board.
config SH_STB1_HARP
bool "STB1_Harp"
config SH_STB1_OVERDRIVE
bool "STB1_Overdrive"
config SH_HP6XX
bool "HP6XX"
help
@ -102,19 +96,6 @@ config SH_HP6XX
More information (hardware only) at
<http://www.hp.com/jornada/>.
config SH_CQREEK
bool "CqREEK"
help
Select CqREEK if configuring for a CqREEK SH7708 or SH7750.
More information at
<http://sources.redhat.com/ecos/hardware.html#SuperH>.
config SH_DMIDA
bool "DMIDA"
help
Select DMIDA if configuring for a DataMyte 4000 Industrial
Digital Assistant. More information at <http://www.dmida.com/>.
config SH_EC3104
bool "EC3104"
help
@ -136,25 +117,9 @@ config SH_DREAMCAST
<http://www.m17n.org/linux-sh/dreamcast/>. There is a
Dreamcast project is at <http://linuxdc.sourceforge.net/>.
config SH_CAT68701
bool "CAT68701"
config SH_BIGSUR
bool "BigSur"
config SH_SH2000
bool "SH2000"
select CPU_SUBTYPE_SH7709
help
SH-2000 is a single-board computer based around SH7709A chip
intended for embedded applications.
It has an Ethernet interface (CS8900A), direct connected
Compact Flash socket, three serial ports and PC-104 bus.
More information at <http://sh2000.sh-linux.org>.
config SH_ADX
bool "ADX"
config SH_MPC1211
bool "Interface MPC1211"
help
@ -246,7 +211,7 @@ source "arch/sh/mm/Kconfig"
config CF_ENABLER
bool "Compact Flash Enabler support"
depends on SH_ADX || SH_SOLUTION_ENGINE || SH_UNKNOWN || SH_CAT68701 || SH_SH03
depends on SH_SOLUTION_ENGINE || SH_UNKNOWN || SH_SH03
---help---
Compact Flash is a small, removable mass storage device introduced
in 1994 originally as a PCMCIA device. If you say `Y' here, you
@ -274,7 +239,7 @@ config CF_AREA5
- "Area5" if CompactFlash is connected to Area 5 (0x14000000)
- "Area6" if it is connected to Area 6 (0x18000000)
"Area6" will work for most boards. For ADX, select "Area5".
"Area6" will work for most boards.
config CF_AREA6
bool "Area6"
@ -418,8 +383,8 @@ source "arch/sh/cchips/Kconfig"
config HEARTBEAT
bool "Heartbeat LED"
depends on SH_MPC1211 || SH_SH03 || SH_CAT68701 || \
SH_STB1_HARP || SH_STB1_OVERDRIVE || SH_BIGSUR || \
depends on SH_MPC1211 || SH_SH03 || \
SH_BIGSUR || \
SH_7751_SOLUTION_ENGINE || SH_7300_SOLUTION_ENGINE || \
SH_73180_SOLUTION_ENGINE || SH_SOLUTION_ENGINE || \
SH_RTS7751R2D || SH_SH4202_MICRODEV || SH_LANDISK

7
arch/sh/Makefile
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@ -90,18 +90,11 @@ machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x
machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) := se/7751
machdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se/7300
machdir-$(CONFIG_SH_73180_SOLUTION_ENGINE) := se/73180
machdir-$(CONFIG_SH_STB1_HARP) := harp
machdir-$(CONFIG_SH_STB1_OVERDRIVE) := overdrive
machdir-$(CONFIG_SH_HP6XX) := hp6xx
machdir-$(CONFIG_SH_CQREEK) := cqreek
machdir-$(CONFIG_SH_DMIDA) := dmida
machdir-$(CONFIG_SH_EC3104) := ec3104
machdir-$(CONFIG_SH_SATURN) := saturn
machdir-$(CONFIG_SH_DREAMCAST) := dreamcast
machdir-$(CONFIG_SH_CAT68701) := cat68701
machdir-$(CONFIG_SH_BIGSUR) := bigsur
machdir-$(CONFIG_SH_SH2000) := sh2000
machdir-$(CONFIG_SH_ADX) := adx
machdir-$(CONFIG_SH_MPC1211) := mpc1211
machdir-$(CONFIG_SH_SH03) := sh03
machdir-$(CONFIG_SH_SECUREEDGE5410) := snapgear

6
arch/sh/boards/adx/Makefile
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@ -1,6 +0,0 @@
#
# Makefile for ADX boards
#
obj-y := setup.o irq.o irq_maskreq.o

31
arch/sh/boards/adx/irq.c
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@ -1,31 +0,0 @@
/*
* linux/arch/sh/boards/adx/irq.c
*
* Copyright (C) 2001 A&D Co., Ltd.
*
* I/O routine and setup routines for A&D ADX Board
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <asm/irq.h>
void init_adx_IRQ(void)
{
int i;
/* printk("init_adx_IRQ()\n");*/
/* setup irq_mask_register */
irq_mask_register = (unsigned short *)0xa6000008;
/* cover all external interrupt area by maskreg_irq_type
* (Actually, irq15 doesn't exist)
*/
for (i = 0; i < 16; i++) {
make_maskreg_irq(i);
disable_irq(i);
}
}

106
arch/sh/boards/adx/irq_maskreg.c
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@ -1,106 +0,0 @@
/*
* linux/arch/sh/kernel/irq_maskreg.c
*
* Copyright (C) 2001 A&D Co., Ltd. <http://www.aandd.co.jp>
*
* This file may be copied or modified under the terms of the GNU
* General Public License. See linux/COPYING for more information.
*
* Interrupt handling for Simple external interrupt mask register
*
* This is for the machine which have single 16 bit register
* for masking external IRQ individually.
* Each bit of the register is for masking each interrupt.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/machvec.h>
/* address of external interrupt mask register
* address must be set prior to use these (maybe in init_XXX_irq())
* XXX : is it better to use .config than specifying it in code? */
unsigned short *irq_mask_register = 0;
/* forward declaration */
static unsigned int startup_maskreg_irq(unsigned int irq);
static void shutdown_maskreg_irq(unsigned int irq);
static void enable_maskreg_irq(unsigned int irq);
static void disable_maskreg_irq(unsigned int irq);
static void mask_and_ack_maskreg(unsigned int);
static void end_maskreg_irq(unsigned int irq);
/* hw_interrupt_type */
static struct hw_interrupt_type maskreg_irq_type = {
.typename = " Mask Register",
.startup = startup_maskreg_irq,
.shutdown = shutdown_maskreg_irq,
.enable = enable_maskreg_irq,
.disable = disable_maskreg_irq,
.ack = mask_and_ack_maskreg,
.end = end_maskreg_irq
};
/* actual implementatin */
static unsigned int startup_maskreg_irq(unsigned int irq)
{
enable_maskreg_irq(irq);
return 0; /* never anything pending */
}
static void shutdown_maskreg_irq(unsigned int irq)
{
disable_maskreg_irq(irq);
}
static void disable_maskreg_irq(unsigned int irq)
{
if (irq_mask_register) {
unsigned long flags;
unsigned short val, mask = 0x01 << irq;
/* Set "irq"th bit */
local_irq_save(flags);
val = ctrl_inw((unsigned long)irq_mask_register);
val |= mask;
ctrl_outw(val, (unsigned long)irq_mask_register);
local_irq_restore(flags);
}
}
static void enable_maskreg_irq(unsigned int irq)
{
if (irq_mask_register) {
unsigned long flags;
unsigned short val, mask = ~(0x01 << irq);
/* Clear "irq"th bit */
local_irq_save(flags);
val = ctrl_inw((unsigned long)irq_mask_register);
val &= mask;
ctrl_outw(val, (unsigned long)irq_mask_register);
local_irq_restore(flags);
}
}
static void mask_and_ack_maskreg(unsigned int irq)
{
disable_maskreg_irq(irq);
}
static void end_maskreg_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_maskreg_irq(irq);
}
void make_maskreg_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].chip = &maskreg_irq_type;
disable_maskreg_irq(irq);
}

56
arch/sh/boards/adx/setup.c
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@ -1,56 +0,0 @@
/*
* linux/arch/sh/board/adx/setup.c
*
* Copyright (C) 2001 A&D Co., Ltd.
*
* I/O routine and setup routines for A&D ADX Board
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <asm/machvec.h>
#include <linux/module.h>
extern void init_adx_IRQ(void);
extern void *cf_io_base;
const char *get_system_type(void)
{
return "A&D ADX";
}
unsigned long adx_isa_port2addr(unsigned long offset)
{
/* CompactFlash (IDE) */
if (((offset >= 0x1f0) && (offset <= 0x1f7)) || (offset == 0x3f6)) {
return (unsigned long)cf_io_base + offset;
}
/* eth0 */
if ((offset >= 0x300) && (offset <= 0x30f)) {
return 0xa5000000 + offset; /* COMM BOARD (AREA1) */
}
return offset + 0xb0000000; /* IOBUS (AREA 4)*/
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_adx __initmv = {
.mv_nr_irqs = 48,
.mv_isa_port2addr = adx_isa_port2addr,
.mv_init_irq = init_adx_IRQ,
};
ALIAS_MV(adx)
int __init platform_setup(void)
{
/* Nothing to see here .. */
return 0;
}

6
arch/sh/boards/cat68701/Makefile
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@ -1,6 +0,0 @@
#
# Makefile for the CAT-68701 specific parts of the kernel
#
obj-y := setup.o irq.o

28
arch/sh/boards/cat68701/irq.c
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@ -1,28 +0,0 @@
/*
* linux/arch/sh/boards/cat68701/irq.c
*
* Copyright (C) 2000 Niibe Yutaka
* 2001 Yutaro Ebihara
*
* Setup routines for A-ONE Corp CAT-68701 SH7708 Board
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <asm/irq.h>
int cat68701_irq_demux(int irq)
{
if(irq==13) return 14;
if(irq==7) return 10;
return irq;
}
void init_cat68701_IRQ()
{
make_imask_irq(10);
make_imask_irq(14);
}

85
arch/sh/boards/cat68701/setup.c
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@ -1,85 +0,0 @@
/*
* linux/arch/sh/boards/cat68701/setup.c
*
* Copyright (C) 2000 Niibe Yutaka
* 2001 Yutaro Ebihara
*
* Setup routines for A-ONE Corp CAT-68701 SH7708 Board
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <asm/io.h>
#include <asm/machvec.h>
#include <asm/mach/io.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
const char *get_system_type(void)
{
return "CAT-68701";
}
#ifdef CONFIG_HEARTBEAT
void heartbeat_cat68701()
{
static unsigned int cnt = 0, period = 0 , bit = 0;
cnt += 1;
if (cnt < period) {
return;
}
cnt = 0;
/* Go through the points (roughly!):
* f(0)=10, f(1)=16, f(2)=20, f(5)=35,f(inf)->110
*/
period = 110 - ( (300<<FSHIFT)/
((avenrun[0]/5) + (3<<FSHIFT)) );
if(bit){ bit=0; }else{ bit=1; }
outw(bit<<15,0x3fe);
}
#endif /* CONFIG_HEARTBEAT */
unsigned long cat68701_isa_port2addr(unsigned long offset)
{
/* CompactFlash (IDE) */
if (((offset >= 0x1f0) && (offset <= 0x1f7)) || (offset==0x3f6))
return 0xba000000 + offset;
/* INPUT PORT */
if ((offset >= 0x3fc) && (offset <= 0x3fd))
return 0xb4007000 + offset;
/* OUTPUT PORT */
if ((offset >= 0x3fe) && (offset <= 0x3ff))
return 0xb4007400 + offset;
return offset + 0xb4000000; /* other I/O (EREA 5)*/
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_cat68701 __initmv = {
.mv_nr_irqs = 32,
.mv_isa_port2addr = cat68701_isa_port2addr,
.mv_irq_demux = cat68701_irq_demux,
.mv_init_irq = init_cat68701_IRQ,
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = heartbeat_cat68701,
#endif
};
ALIAS_MV(cat68701)
int __init platform_setup(void)
{
/* dummy read erea5 (CS8900A) */
}

6
arch/sh/boards/cqreek/Makefile
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@ -1,6 +0,0 @@
#
# Makefile for the CqREEK specific parts of the kernel
#
obj-y := setup.o irq.o

128
arch/sh/boards/cqreek/irq.c
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@ -1,128 +0,0 @@
/* $Id: irq.c,v 1.1.2.4 2002/11/04 20:33:56 lethal Exp $
*
* arch/sh/boards/cqreek/irq.c
*
* Copyright (C) 2000 Niibe Yutaka
*
* CqREEK IDE/ISA Bridge Support.
*
*/
#include <linux/irq.h>
#include <linux/init.h>
#include <asm/cqreek/cqreek.h>
#include <asm/io.h>
#include <asm/io_generic.h>
#include <asm/irq.h>
#include <asm/machvec.h>
#include <asm/machvec_init.h>
#include <asm/rtc.h>
struct cqreek_irq_data {
unsigned short mask_port; /* Port of Interrupt Mask Register */
unsigned short stat_port; /* Port of Interrupt Status Register */
unsigned short bit; /* Value of the bit */
};
static struct cqreek_irq_data cqreek_irq_data[NR_IRQS];
static void disable_cqreek_irq(unsigned int irq)
{
unsigned long flags;
unsigned short mask;
unsigned short mask_port = cqreek_irq_data[irq].mask_port;
unsigned short bit = cqreek_irq_data[irq].bit;
local_irq_save(flags);
/* Disable IRQ */
mask = inw(mask_port) & ~bit;
outw_p(mask, mask_port);
local_irq_restore(flags);
}
static void enable_cqreek_irq(unsigned int irq)
{
unsigned long flags;
unsigned short mask;
unsigned short mask_port = cqreek_irq_data[irq].mask_port;
unsigned short bit = cqreek_irq_data[irq].bit;
local_irq_save(flags);
/* Enable IRQ */
mask = inw(mask_port) | bit;
outw_p(mask, mask_port);
local_irq_restore(flags);
}
static void mask_and_ack_cqreek(unsigned int irq)
{
unsigned short stat_port = cqreek_irq_data[irq].stat_port;
unsigned short bit = cqreek_irq_data[irq].bit;
disable_cqreek_irq(irq);
/* Clear IRQ (it might be edge IRQ) */
inw(stat_port);
outw_p(bit, stat_port);
}
static void end_cqreek_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_cqreek_irq(irq);
}
static unsigned int startup_cqreek_irq(unsigned int irq)
{
enable_cqreek_irq(irq);
return 0;
}
static void shutdown_cqreek_irq(unsigned int irq)
{
disable_cqreek_irq(irq);
}
static struct hw_interrupt_type cqreek_irq_type = {
.typename = "CqREEK-IRQ",
.startup = startup_cqreek_irq,
.shutdown = shutdown_cqreek_irq,
.enable = enable_cqreek_irq,
.disable = disable_cqreek_irq,
.ack = mask_and_ack_cqreek,
.end = end_cqreek_irq
};
int cqreek_has_ide, cqreek_has_isa;
/* XXX: This is just for test for my NE2000 ISA board
What we really need is virtualized IRQ and demultiplexer like HP600 port */
void __init init_cqreek_IRQ(void)
{
if (cqreek_has_ide) {
cqreek_irq_data[14].mask_port = BRIDGE_IDE_INTR_MASK;
cqreek_irq_data[14].stat_port = BRIDGE_IDE_INTR_STAT;
cqreek_irq_data[14].bit = 1;
irq_desc[14].chip = &cqreek_irq_type;
irq_desc[14].status = IRQ_DISABLED;
irq_desc[14].action = 0;
irq_desc[14].depth = 1;
disable_cqreek_irq(14);
}
if (cqreek_has_isa) {
cqreek_irq_data[10].mask_port = BRIDGE_ISA_INTR_MASK;
cqreek_irq_data[10].stat_port = BRIDGE_ISA_INTR_STAT;
cqreek_irq_data[10].bit = (1 << 10);
/* XXX: Err... we may need demultiplexer for ISA irq... */
irq_desc[10].chip = &cqreek_irq_type;
irq_desc[10].status = IRQ_DISABLED;
irq_desc[10].action = 0;
irq_desc[10].depth = 1;
disable_cqreek_irq(10);
}
}

100
arch/sh/boards/cqreek/setup.c
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@ -1,100 +0,0 @@
/* $Id: setup.c,v 1.5 2003/08/04 01:51:58 lethal Exp $
*
* arch/sh/kernel/setup_cqreek.c
*
* Copyright (C) 2000 Niibe Yutaka
*
* CqREEK IDE/ISA Bridge Support.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/mach/cqreek.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/io_generic.h>
#include <asm/irq.h>
#include <asm/rtc.h>
#define IDE_OFFSET 0xA4000000UL
#define ISA_OFFSET 0xA4A00000UL
const char *get_system_type(void)
{
return "CqREEK";
}
static unsigned long cqreek_port2addr(unsigned long port)
{
if (0x0000<=port && port<=0x0040)
return IDE_OFFSET + port;
if ((0x01f0<=port && port<=0x01f7) || port == 0x03f6)
return IDE_OFFSET + port;
return ISA_OFFSET + port;
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_cqreek __initmv = {
#if defined(CONFIG_CPU_SH4)
.mv_nr_irqs = 48,
#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
.mv_nr_irqs = 32,
#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
.mv_nr_irqs = 61,
#endif
.mv_init_irq = init_cqreek_IRQ,
.mv_isa_port2addr = cqreek_port2addr,
};
ALIAS_MV(cqreek)
/*
* Initialize the board
*/
void __init platform_setup(void)
{
int i;
/* udelay is not available at setup time yet... */
#define DELAY() do {for (i=0; i<10000; i++) ctrl_inw(0xa0000000);} while(0)
if ((inw (BRIDGE_FEATURE) & 1)) { /* We have IDE interface */
outw_p(0, BRIDGE_IDE_INTR_LVL);
outw_p(0, BRIDGE_IDE_INTR_MASK);
outw_p(0, BRIDGE_IDE_CTRL);
DELAY();
outw_p(0x8000, BRIDGE_IDE_CTRL);
DELAY();
outw_p(0xffff, BRIDGE_IDE_INTR_STAT); /* Clear interrupt status */
outw_p(0x0f-14, BRIDGE_IDE_INTR_LVL); /* Use 14 IPR */
outw_p(1, BRIDGE_IDE_INTR_MASK); /* Enable interrupt */
cqreek_has_ide=1;
}
if ((inw (BRIDGE_FEATURE) & 2)) { /* We have ISA interface */
outw_p(0, BRIDGE_ISA_INTR_LVL);
outw_p(0, BRIDGE_ISA_INTR_MASK);
outw_p(0, BRIDGE_ISA_CTRL);
DELAY();
outw_p(0x8000, BRIDGE_ISA_CTRL);
DELAY();
outw_p(0xffff, BRIDGE_ISA_INTR_STAT); /* Clear interrupt status */
outw_p(0x0f-10, BRIDGE_ISA_INTR_LVL); /* Use 10 IPR */
outw_p(0xfff8, BRIDGE_ISA_INTR_MASK); /* Enable interrupt */
cqreek_has_isa=1;
}
printk(KERN_INFO "CqREEK Setup (IDE=%d, ISA=%d)...done\n", cqreek_has_ide, cqreek_has_isa);
}

7
arch/sh/boards/dmida/Makefile
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@ -1,7 +0,0 @@
#
# Makefile for the DataMyte Industrial Digital Assistant(tm) specific parts
# of the kernel
#
obj-y := mach.o

59
arch/sh/boards/dmida/mach.c
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@ -1,59 +0,0 @@
/*
* linux/arch/sh/boards/dmida/mach.c
*
* by Greg Banks <gbanks@pocketpenguins.com>
* (c) 2000 PocketPenguins Inc
*
* Derived from mach_hp600.c, which bore the message:
* Copyright (C) 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Machine vector for the DataMyte Industrial Digital Assistant(tm).
* See http://www.dmida.com
*
*/
#include <linux/init.h>
#include <asm/machvec.h>
#include <asm/rtc.h>
#include <asm/machvec_init.h>
#include <asm/io.h>
#include <asm/hd64465/hd64465.h>
#include <asm/irq.h>
/*
* The Machine Vector
*/
struct sh_machine_vector mv_dmida __initmv = {
.mv_nr_irqs = HD64465_IRQ_BASE+HD64465_IRQ_NUM,
.mv_inb = hd64465_inb,
.mv_inw = hd64465_inw,
.mv_inl = hd64465_inl,
.mv_outb = hd64465_outb,
.mv_outw = hd64465_outw,
.mv_outl = hd64465_outl,
.mv_inb_p = hd64465_inb_p,
.mv_inw_p = hd64465_inw,
.mv_inl_p = hd64465_inl,
.mv_outb_p = hd64465_outb_p,
.mv_outw_p = hd64465_outw,
.mv_outl_p = hd64465_outl,
.mv_insb = hd64465_insb,
.mv_insw = hd64465_insw,
.mv_insl = hd64465_insl,
.mv_outsb = hd64465_outsb,
.mv_outsw = hd64465_outsw,
.mv_outsl = hd64465_outsl,
.mv_irq_demux = hd64465_irq_demux,
};
ALIAS_MV(dmida)

8
arch/sh/boards/harp/Makefile
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@ -1,8 +0,0 @@
#
# Makefile for STMicroelectronics board specific parts of the kernel
#
obj-y := irq.o setup.o mach.o led.o
obj-$(CONFIG_PCI) += pcidma.o

147
arch/sh/boards/harp/irq.c
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@ -1,147 +0,0 @@
/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Looks after interrupts on the HARP board.
*
* Bases on the IPR irq system
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/harp/harp.h>
#define NUM_EXTERNAL_IRQS 16
// Early versions of the STB1 Overdrive required this nasty frig
//#define INVERT_INTMASK_WRITES
static void enable_harp_irq(unsigned int irq);
static void disable_harp_irq(unsigned int irq);
/* shutdown is same as "disable" */
#define shutdown_harp_irq disable_harp_irq
static void mask_and_ack_harp(unsigned int);
static void end_harp_irq(unsigned int irq);
static unsigned int startup_harp_irq(unsigned int irq)
{
enable_harp_irq(irq);
return 0; /* never anything pending */
}
static struct hw_interrupt_type harp_irq_type = {
.typename = "Harp-IRQ",
.startup = startup_harp_irq,
.shutdown = shutdown_harp_irq,
.enable = enable_harp_irq,
.disable = disable_harp_irq,
.ack = mask_and_ack_harp,
.end = end_harp_irq
};
static void disable_harp_irq(unsigned int irq)
{
unsigned val, flags;
unsigned maskReg;
unsigned mask;
int pri;
if (irq < 0 || irq >= NUM_EXTERNAL_IRQS)
return;
pri = 15 - irq;
if (pri < 8) {
maskReg = EPLD_INTMASK0;
} else {
maskReg = EPLD_INTMASK1;
pri -= 8;
}
local_irq_save(flags);
mask = ctrl_inl(maskReg);
mask &= (~(1 << pri));
#if defined(INVERT_INTMASK_WRITES)
mask ^= 0xff;
#endif
ctrl_outl(mask, maskReg);
local_irq_restore(flags);
}
static void enable_harp_irq(unsigned int irq)
{
unsigned flags;
unsigned maskReg;
unsigned mask;
int pri;
if (irq < 0 || irq >= NUM_EXTERNAL_IRQS)
return;
pri = 15 - irq;
if (pri < 8) {
maskReg = EPLD_INTMASK0;
} else {
maskReg = EPLD_INTMASK1;
pri -= 8;
}
local_irq_save(flags);
mask = ctrl_inl(maskReg);
mask |= (1 << pri);
#if defined(INVERT_INTMASK_WRITES)
mask ^= 0xff;
#endif
ctrl_outl(mask, maskReg);
local_irq_restore(flags);
}
/* This functions sets the desired irq handler to be an overdrive type */
static void __init make_harp_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].chip = &harp_irq_type;
disable_harp_irq(irq);
}
static void mask_and_ack_harp(unsigned int irq)
{
disable_harp_irq(irq);
}
static void end_harp_irq(unsigned int irq)
{
enable_harp_irq(irq);
}
void __init init_harp_irq(void)
{
int i;
#if !defined(INVERT_INTMASK_WRITES)
// On the harp these are set to enable an interrupt
ctrl_outl(0x00, EPLD_INTMASK0);
ctrl_outl(0x00, EPLD_INTMASK1);
#else
// On the Overdrive the data is inverted before being stored in the reg
ctrl_outl(0xff, EPLD_INTMASK0);
ctrl_outl(0xff, EPLD_INTMASK1);
#endif
for (i = 0; i < NUM_EXTERNAL_IRQS; i++) {
make_harp_irq(i);
}
}

51
arch/sh/boards/harp/led.c
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@ -1,51 +0,0 @@
/*
* linux/arch/sh/stboards/led.c
*
* Copyright (C) 2000 Stuart Menefy <stuart.menefy@st.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* This file contains ST40STB1 HARP and compatible code.
*/
#include <asm/io.h>
#include <asm/harp/harp.h>
/* Harp: Flash LD10 (front pannel) connected to EPLD (IC8) */
/* Overdrive: Flash LD1 (front panel) connected to EPLD (IC4) */
/* Works for HARP and overdrive */
static void mach_led(int position, int value)
{
if (value) {
ctrl_outl(EPLD_LED_ON, EPLD_LED);
} else {
ctrl_outl(EPLD_LED_OFF, EPLD_LED);
}
}
#ifdef CONFIG_HEARTBEAT
#include <linux/sched.h>
/* acts like an actual heart beat -- ie thump-thump-pause... */
void heartbeat_harp(void)
{
static unsigned cnt = 0, period = 0, dist = 0;
if (cnt == 0 || cnt == dist)
mach_led( -1, 1);
else if (cnt == 7 || cnt == dist+7)
mach_led( -1, 0);
if (++cnt > period) {
cnt = 0;
/* The hyperbolic function below modifies the heartbeat period
* length in dependency of the current (5min) load. It goes
* through the points f(0)=126, f(1)=86, f(5)=51,
* f(inf)->30. */
period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
dist = period / 4;
}
}
#endif

62
arch/sh/boards/harp/mach.c
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@ -1,62 +0,0 @@
/*
* linux/arch/sh/boards/harp/mach.c
*
* Copyright (C) 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Machine vector for the STMicroelectronics STB1 HARP and compatible boards
*/
#include <linux/init.h>
#include <asm/machvec.h>
#include <asm/rtc.h>
#include <asm/machvec_init.h>
#include <asm/hd64465/io.h>
#include <asm/hd64465/hd64465.h>
void setup_harp(void);
void init_harp_irq(void);
void heartbeat_harp(void);
/*
* The Machine Vector
*/
struct sh_machine_vector mv_harp __initmv = {
.mv_nr_irqs = 89 + HD64465_IRQ_NUM,
.mv_inb = hd64465_inb,
.mv_inw = hd64465_inw,
.mv_inl = hd64465_inl,
.mv_outb = hd64465_outb,
.mv_outw = hd64465_outw,
.mv_outl = hd64465_outl,
.mv_inb_p = hd64465_inb_p,
.mv_inw_p = hd64465_inw,
.mv_inl_p = hd64465_inl,
.mv_outb_p = hd64465_outb_p,
.mv_outw_p = hd64465_outw,
.mv_outl_p = hd64465_outl,
.mv_insb = hd64465_insb,
.mv_insw = hd64465_insw,
.mv_insl = hd64465_insl,
.mv_outsb = hd64465_outsb,
.mv_outsw = hd64465_outsw,
.mv_outsl = hd64465_outsl,
.mv_isa_port2addr = hd64465_isa_port2addr,
#ifdef CONFIG_PCI
.mv_init_irq = init_harp_irq,
#endif
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = heartbeat_harp,
#endif
};
ALIAS_MV(harp)

42
arch/sh/boards/harp/pcidma.c
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@ -1,42 +0,0 @@
/*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Dynamic DMA mapping support.
*/
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <asm/addrspace.h>
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t * dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
/* Is it neccessary to do the memset? */
memset(ret, 0, size);
*dma_handle = virt_to_bus(ret);
}
/* We must flush the cache before we pass it on to the device */
flush_cache_all();
return P2SEGADDR(ret);
}
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
unsigned long p1addr=P1SEGADDR((unsigned long)vaddr);
free_pages(p1addr, get_order(size));
}

90
arch/sh/boards/harp/setup.c
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/*
* arch/sh/stboard/setup.c
*
* Copyright (C) 2001 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* STMicroelectronics ST40STB1 HARP and compatible support.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/harp/harp.h>
const char *get_system_type(void)
{
return "STB1 Harp";
}
/*
* Initialize the board
*/
int __init platform_setup(void)
{
#ifdef CONFIG_SH_STB1_HARP
unsigned long ic8_version, ic36_version;
ic8_version = ctrl_inl(EPLD_REVID2);
ic36_version = ctrl_inl(EPLD_REVID1);
printk("STMicroelectronics STB1 HARP initialisaton\n");
printk("EPLD versions: IC8: %d.%02d, IC36: %d.%02d\n",
(ic8_version >> 4) & 0xf, ic8_version & 0xf,
(ic36_version >> 4) & 0xf, ic36_version & 0xf);
#elif defined(CONFIG_SH_STB1_OVERDRIVE)
unsigned long version;
version = ctrl_inl(EPLD_REVID);
printk("STMicroelectronics STB1 Overdrive initialisaton\n");
printk("EPLD version: %d.%02d\n",
(version >> 4) & 0xf, version & 0xf);
#else
#error Undefined machine
#endif
/* Currently all STB1 chips have problems with the sleep instruction,
* so disable it here.
*/
disable_hlt();
return 0;
}
/*
* pcibios_map_platform_irq
*
* This is board specific and returns the IRQ for a given PCI device.
* It is used by the PCI code (arch/sh/kernel/st40_pci*)
*
*/
#define HARP_PCI_IRQ 1
#define HARP_BRIDGE_IRQ 2
#define OVERDRIVE_SLOT0_IRQ 0
int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
switch (slot) {
#ifdef CONFIG_SH_STB1_HARP
case 2: /*This is the PCI slot on the */
return HARP_PCI_IRQ;
case 1: /* this is the bridge */
return HARP_BRIDGE_IRQ;
#elif defined(CONFIG_SH_STB1_OVERDRIVE)
case 1:
case 2:
case 3:
return slot - 1;
#else
#error Unknown board
#endif
default:
return -1;
}
}

8
arch/sh/boards/overdrive/Makefile
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@ -1,8 +0,0 @@
#
# Makefile for the STMicroelectronics Overdrive specific parts of the kernel
#
obj-y := mach.o setup.o io.o irq.o led.o
obj-$(CONFIG_PCI) += fpga.o galileo.o pcidma.o

133
arch/sh/boards/overdrive/fpga.c
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/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* This file handles programming up the Altera Flex10K that interfaces to
* the Galileo, and does the PS/2 keyboard and mouse
*
*/
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <asm/overdriver/gt64111.h>
#include <asm/overdrive/overdrive.h>
#include <asm/overdrive/fpga.h>
#define FPGA_NotConfigHigh() (*FPGA_ControlReg) = (*FPGA_ControlReg) | ENABLE_FPGA_BIT
#define FPGA_NotConfigLow() (*FPGA_ControlReg) = (*FPGA_ControlReg) & RESET_FPGA_MASK
/* I need to find out what (if any) the real delay factor here is */
/* The delay is definately not critical */
#define long_delay() {int i;for(i=0;i<10000;i++);}
#define short_delay() {int i;for(i=0;i<100;i++);}
static void __init program_overdrive_fpga(const unsigned char *fpgacode,
int size)
{
int timeout = 0;
int i, j;
unsigned char b;
static volatile unsigned char *FPGA_ControlReg =
(volatile unsigned char *) (OVERDRIVE_CTRL);
static volatile unsigned char *FPGA_ProgramReg =
(volatile unsigned char *) (FPGA_DCLK_ADDRESS);
printk("FPGA: Commencing FPGA Programming\n");
/* The PCI reset but MUST be low when programming the FPGA !!! */
b = (*FPGA_ControlReg) & RESET_PCI_MASK;
(*FPGA_ControlReg) = b;
/* Prepare FPGA to program */
FPGA_NotConfigHigh();
long_delay();
FPGA_NotConfigLow();
short_delay();
while ((*FPGA_ProgramReg & FPGA_NOT_STATUS) != 0) {
printk("FPGA: Waiting for NotStatus to go Low ... \n");
}
FPGA_NotConfigHigh();
/* Wait for FPGA "ready to be programmed" signal */
printk("FPGA: Waiting for NotStatus to go high (FPGA ready)... \n");
for (timeout = 0;
(((*FPGA_ProgramReg & FPGA_NOT_STATUS) == 0)
&& (timeout < FPGA_TIMEOUT)); timeout++);
/* Check if timeout condition occured - i.e. an error */
if (timeout == FPGA_TIMEOUT) {
printk
("FPGA: Failed to program - Timeout waiting for notSTATUS to go high\n");
return;
}
printk("FPGA: Copying data to FPGA ... %d bytes\n", size);
/* Copy array to FPGA - bit at a time */
for (i = 0; i < size; i++) {
volatile unsigned w = 0;
for (j = 0; j < 8; j++) {
*FPGA_ProgramReg = (fpgacode[i] >> j) & 0x01;
short_delay();
}
if ((i & 0x3ff) == 0) {
printk(".");
}
}
/* Waiting for CONFDONE to go high - means the program is complete */
for (timeout = 0;
(((*FPGA_ProgramReg & FPGA_CONFDONE) == 0)
&& (timeout < FPGA_TIMEOUT)); timeout++) {
*FPGA_ProgramReg = 0x0;
long_delay();
}
if (timeout == FPGA_TIMEOUT) {
printk
("FPGA: Failed to program - Timeout waiting for CONFDONE to go high\n");
return;
} else { /* Clock another 10 times - gets the device into a working state */
for (i = 0; i < 10; i++) {
*FPGA_ProgramReg = 0x0;
short_delay();
}
}
printk("FPGA: Programming complete\n");
}
static const unsigned char __init fpgacode[] = {
#include "./overdrive.ttf" /* Code from maxplus2 compiler */
, 0, 0
};
int __init init_overdrive_fpga(void)
{
program_overdrive_fpga(fpgacode, sizeof(fpgacode));
return 0;
}

587
arch/sh/boards/overdrive/galileo.c
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/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* This file contains the PCI routines required for the Galileo GT6411
* PCI bridge as used on the Orion and Overdrive boards.
*
*/
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <asm/overdrive/overdrive.h>
#include <asm/overdrive/gt64111.h>
/* After boot, we shift the Galileo registers so that they appear
* in BANK6, along with IO space. This means we can have one contingous
* lump of PCI address space without these registers appearing in the
* middle of them
*/
#define GT64111_BASE_ADDRESS 0xbb000000
#define GT64111_IO_BASE_ADDRESS 0x1000
/* The GT64111 registers appear at this address to the SH4 after reset */
#define RESET_GT64111_BASE_ADDRESS 0xb4000000
/* Macros used to access the Galileo registers */
#define RESET_GT64111_REG(x) (RESET_GT64111_BASE_ADDRESS+x)
#define GT64111_REG(x) (GT64111_BASE_ADDRESS+x)
#define RESET_GT_WRITE(x,v) writel((v),RESET_GT64111_REG(x))
#define RESET_GT_READ(x) readl(RESET_GT64111_REG(x))
#define GT_WRITE(x,v) writel((v),GT64111_REG(x))
#define GT_WRITE_BYTE(x,v) writeb((v),GT64111_REG(x))
#define GT_WRITE_SHORT(x,v) writew((v),GT64111_REG(x))
#define GT_READ(x) readl(GT64111_REG(x))
#define GT_READ_BYTE(x) readb(GT64111_REG(x))
#define GT_READ_SHORT(x) readw(GT64111_REG(x))
/* Where the various SH banks start at */
#define SH_BANK4_ADR 0xb0000000
#define SH_BANK5_ADR 0xb4000000
#define SH_BANK6_ADR 0xb8000000
/* Masks out everything but lines 28,27,26 */
#define BANK_SELECT_MASK 0x1c000000
#define SH4_TO_BANK(x) ( (x) & BANK_SELECT_MASK)
/*
* Masks used for address conversaion. Bank 6 is used for IO and
* has all the address bits zeroed by the FPGA. Special case this
*/
#define MEMORY_BANK_MASK 0x1fffffff
#define IO_BANK_MASK 0x03ffffff
/* Mark bank 6 as the bank used for IO. You can change this in the FPGA code
* if you want
*/
#define IO_BANK_ADR PCI_GTIO_BASE
/* Will select the correct mask to apply depending on the SH$ address */
#define SELECT_BANK_MASK(x) \
( (SH4_TO_BANK(x)==SH4_TO_BANK(IO_BANK_ADR)) ? IO_BANK_MASK : MEMORY_BANK_MASK)
/* Converts between PCI space and P2 region */
#define SH4_TO_PCI(x) ((x)&SELECT_BANK_MASK(x))
/* Various macros for figuring out what to stick in the Galileo registers.
* You *really* don't want to figure this stuff out by hand, you always get
* it wrong
*/
#define GT_MEM_LO_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7ff)
#define GT_MEM_HI_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7f)
#define GT_MEM_SUB_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>20)&0xff)
#define PROGRAM_HI_LO(block,a,s) \
GT_WRITE(block##_LO_DEC_ADR,GT_MEM_LO_ADR(a));\
GT_WRITE(block##_HI_DEC_ADR,GT_MEM_HI_ADR(a+s-1))
#define PROGRAM_SUB_HI_LO(block,a,s) \
GT_WRITE(block##_LO_DEC_ADR,GT_MEM_SUB_ADR(a));\
GT_WRITE(block##_HI_DEC_ADR,GT_MEM_SUB_ADR(a+s-1))
/* We need to set the size, and the offset register */
#define GT_BAR_MASK(x) ((x)&~0xfff)
/* Macro to set up the BAR in the Galileo. Essentially used for the DRAM */
#define PROGRAM_GT_BAR(block,a,s) \
GT_WRITE(PCI_##block##_BANK_SIZE,GT_BAR_MASK((s-1)));\
write_config_to_galileo(PCI_CONFIG_##block##_BASE_ADR,\
GT_BAR_MASK(a))
#define DISABLE_GT_BAR(block) \
GT_WRITE(PCI_##block##_BANK_SIZE,0),\
GT_CONFIG_WRITE(PCI_CONFIG_##block##_BASE_ADR,\
0x80000000)
/* Macros to disable things we are not going to use */
#define DISABLE_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0x7ff);\
GT_WRITE(x##_HI_DEC_ADR,0x00)
#define DISABLE_SUB_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0xff);\
GT_WRITE(x##_HI_DEC_ADR,0x00)
static void __init reset_pci(void)
{
/* Set RESET_PCI bit high */
writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
udelay(250);
/* Set RESET_PCI bit low */
writeb(readb(OVERDRIVE_CTRL) & RESET_PCI_MASK, OVERDRIVE_CTRL);
udelay(250);
writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
udelay(250);
}
static int write_config_to_galileo(int where, u32 val);
#define GT_CONFIG_WRITE(where,val) write_config_to_galileo(where,val)
#define ENABLE_PCI_DRAM
#ifdef TEST_DRAM
/* Test function to check out if the PCI DRAM is working OK */
static int /* __init */ test_dram(unsigned *base, unsigned size)
{
unsigned *p = base;
unsigned *end = (unsigned *) (((unsigned) base) + size);
unsigned w;
for (p = base; p < end; p++) {
*p = 0xffffffff;
if (*p != 0xffffffff) {
printk("AAARGH -write failed!!! at %p is %x\n", p,
*p);
return 0;
}
*p = 0x0;
if (*p != 0x0) {
printk("AAARGH -write failed!!!\n");
return 0;
}
}
for (p = base; p < end; p++) {
*p = (unsigned) p;
if (*p != (unsigned) p) {
printk("Failed at 0x%p, actually is 0x%x\n", p,
*p);
return 0;
}
}
for (p = base; p < end; p++) {
w = ((unsigned) p & 0xffff0000);
*p = w | (w >> 16);
}
for (p = base; p < end; p++) {
w = ((unsigned) p & 0xffff0000);
w |= (w >> 16);
if (*p != w) {
printk
("Failed at 0x%p, should be 0x%x actually is 0x%x\n",
p, w, *p);
return 0;
}
}
return 1;
}
#endif
/* Function to set up and initialise the galileo. This sets up the BARS,
* maps the DRAM into the address space etc,etc
*/
int __init galileo_init(void)
{
reset_pci();
/* Now shift the galileo regs into this block */
RESET_GT_WRITE(INTERNAL_SPACE_DEC,
GT_MEM_LO_ADR(GT64111_BASE_ADDRESS));
/* Should have a sanity check here, that you can read back at the new
* address what you just wrote
*/
/* Disable decode for all regions */
DISABLE_DECODE(RAS10);
DISABLE_DECODE(RAS32);
DISABLE_DECODE(CS20);
DISABLE_DECODE(CS3);
DISABLE_DECODE(PCI_IO);
DISABLE_DECODE(PCI_MEM0);
DISABLE_DECODE(PCI_MEM1);
/* Disable all BARS */
GT_WRITE(BAR_ENABLE_ADR, 0x1ff);
DISABLE_GT_BAR(RAS10);
DISABLE_GT_BAR(RAS32);
DISABLE_GT_BAR(CS20);
DISABLE_GT_BAR(CS3);
/* Tell the BAR where the IO registers now are */
GT_CONFIG_WRITE(PCI_CONFIG_INT_REG_IO_ADR,GT_BAR_MASK(
(GT64111_IO_BASE_ADDRESS &
IO_BANK_MASK)));
/* set up a 112 Mb decode */
PROGRAM_HI_LO(PCI_MEM0, SH_BANK4_ADR, 112 * 1024 * 1024);
/* Set up a 32 MB io space decode */
PROGRAM_HI_LO(PCI_IO, IO_BANK_ADR, 32 * 1024 * 1024);
#ifdef ENABLE_PCI_DRAM
/* Program up the DRAM configuration - there is DRAM only in bank 0 */
/* Now set up the DRAM decode */
PROGRAM_HI_LO(RAS10, PCI_DRAM_BASE, PCI_DRAM_SIZE);
/* And the sub decode */
PROGRAM_SUB_HI_LO(RAS0, PCI_DRAM_BASE, PCI_DRAM_SIZE);
DISABLE_SUB_DECODE(RAS1);
/* Set refresh rate */
GT_WRITE(DRAM_BANK0_PARMS, 0x3f);
GT_WRITE(DRAM_CFG, 0x100);
/* we have to lob off the top bits rememeber!! */
PROGRAM_GT_BAR(RAS10, SH4_TO_PCI(PCI_DRAM_BASE), PCI_DRAM_SIZE);
#endif
/* We are only interested in decoding RAS10 and the Galileo's internal
* registers (as IO) on the PCI bus
*/
#ifdef ENABLE_PCI_DRAM
GT_WRITE(BAR_ENABLE_ADR, (~((1 << 8) | (1 << 3))) & 0x1ff);
#else
GT_WRITE(BAR_ENABLE_ADR, (~(1 << 3)) & 0x1ff);
#endif
/* Change the class code to host bridge, it actually powers up
* as a memory controller
*/
GT_CONFIG_WRITE(8, 0x06000011);
/* Allow the galileo to master the PCI bus */
GT_CONFIG_WRITE(PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_IO);
#if 0
printk("Testing PCI DRAM - ");
if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
printk("Passed\n");
}else {
printk("FAILED\n");
}
#endif
return 0;
}
#define SET_CONFIG_BITS(bus,devfn,where)\
((1<<31) | ((bus) << 16) | ((devfn) << 8) | ((where) & ~3))
#define CONFIG_CMD(dev, where) SET_CONFIG_BITS((dev)->bus->number,(dev)->devfn,where)
/* This write to the galileo config registers, unlike the functions below, can
* be used before the PCI subsystem has started up
*/
static int __init write_config_to_galileo(int where, u32 val)
{
GT_WRITE(PCI_CFG_ADR, SET_CONFIG_BITS(0, 0, where));
GT_WRITE(PCI_CFG_DATA, val);
return 0;
}
/* We exclude the galileo and slot 31, the galileo because I don't know how to stop
* the setup code shagging up the setup I have done on it, and 31 because the whole
* thing locks up if you try to access that slot (which doesn't exist of course anyway
*/
#define EXCLUDED_DEV(dev) ((dev->bus->number==0) && ((PCI_SLOT(dev->devfn)==0) || (PCI_SLOT(dev->devfn) == 31)))
static int galileo_read_config_byte(struct pci_dev *dev, int where,
u8 * val)
{
/* I suspect this doesn't work because this drives a special cycle ? */
if (EXCLUDED_DEV(dev)) {
*val = 0xff;
return PCIBIOS_SUCCESSFUL;
}
/* Start the config cycle */
GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
/* Read back the result */
*val = GT_READ_BYTE(PCI_CFG_DATA + (where & 3));
return PCIBIOS_SUCCESSFUL;
}
static int galileo_read_config_word(struct pci_dev *dev, int where,
u16 * val)
{
if (EXCLUDED_DEV(dev)) {
*val = 0xffff;
return PCIBIOS_SUCCESSFUL;
}
GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
*val = GT_READ_SHORT(PCI_CFG_DATA + (where & 2));
return PCIBIOS_SUCCESSFUL;
}
static int galileo_read_config_dword(struct pci_dev *dev, int where,
u32 * val)
{
if (EXCLUDED_DEV(dev)) {
*val = 0xffffffff;
return PCIBIOS_SUCCESSFUL;
}
GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
*val = GT_READ(PCI_CFG_DATA);
return PCIBIOS_SUCCESSFUL;
}
static int galileo_write_config_byte(struct pci_dev *dev, int where,
u8 val)
{
GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
GT_WRITE_BYTE(PCI_CFG_DATA + (where & 3), val);
return PCIBIOS_SUCCESSFUL;
}
static int galileo_write_config_word(struct pci_dev *dev, int where,
u16 val)
{
GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
GT_WRITE_SHORT(PCI_CFG_DATA + (where & 2), val);
return PCIBIOS_SUCCESSFUL;
}
static int galileo_write_config_dword(struct pci_dev *dev, int where,
u32 val)
{
GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
GT_WRITE(PCI_CFG_DATA, val);
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops pci_config_ops = {
galileo_read_config_byte,
galileo_read_config_word,
galileo_read_config_dword,
galileo_write_config_byte,
galileo_write_config_word,
galileo_write_config_dword
};
/* Everything hangs off this */
static struct pci_bus *pci_root_bus;
static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
{
return PCI_SLOT(dev->devfn);
}
static int __init map_od_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
/* Slot 1: Galileo
* Slot 2: PCI Slot 1
* Slot 3: PCI Slot 2
* Slot 4: ESS
*/
switch (slot) {
case 2:
return OVERDRIVE_PCI_IRQ1;
case 3:
/* Note this assumes you have a hacked card in slot 2 */
return OVERDRIVE_PCI_IRQ2;
case 4:
return OVERDRIVE_ESS_IRQ;
default:
/* printk("PCI: Unexpected IRQ mapping request for slot %d\n", slot); */
return -1;
}
}
void __init
pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
{
ranges->io_start -= bus->resource[0]->start;
ranges->io_end -= bus->resource[0]->start;
ranges->mem_start -= bus->resource[1]->start;
ranges->mem_end -= bus->resource[1]->start;
}
static void __init pci_fixup_ide_bases(struct pci_dev *d)
{
int i;
/*
* PCI IDE controllers use non-standard I/O port decoding, respect it.
*/
if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
return;
printk("PCI: IDE base address fixup for %s\n", pci_name(d));
for(i=0; i<4; i++) {
struct resource *r = &d->resource[i];
if ((r->start & ~0x80) == 0x374) {
r->start |= 2;
r->end = r->start;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
void __init pcibios_init(void)
{
static struct resource galio,galmem;
/* Allocate the registers used by the Galileo */
galio.flags = IORESOURCE_IO;
galio.name = "Galileo GT64011";
galmem.flags = IORESOURCE_MEM|IORESOURCE_PREFETCH;
galmem.name = "Galileo GT64011 DRAM";
allocate_resource(&ioport_resource, &galio, 256,
GT64111_IO_BASE_ADDRESS,GT64111_IO_BASE_ADDRESS+256, 256, NULL, NULL);
allocate_resource(&iomem_resource, &galmem,PCI_DRAM_SIZE,
PHYSADDR(PCI_DRAM_BASE), PHYSADDR(PCI_DRAM_BASE)+PCI_DRAM_SIZE,
PCI_DRAM_SIZE, NULL, NULL);
/* ok, do the scan man */
pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
pci_assign_unassigned_resources();
pci_fixup_irqs(no_swizzle, map_od_irq);
#ifdef TEST_DRAM
printk("Testing PCI DRAM - ");
if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
printk("Passed\n");
}else {
printk("FAILED\n");
}
#endif
}
char * __init pcibios_setup(char *str)
{
return str;
}
int pcibios_enable_device(struct pci_dev *dev)
{
u16 cmd, old_cmd;
int idx;
struct resource *r;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
for (idx = 0; idx < 6; idx++) {
r = dev->resource + idx;
if (!r->start && r->end) {
printk(KERN_ERR
"PCI: Device %s not available because"
" of resource collisions\n",
pci_name(dev));
return -EINVAL;
}
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
if (cmd != old_cmd) {
printk("PCI: enabling device %s (%04x -> %04x)\n",
pci_name(dev), old_cmd, cmd);
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
return 0;
}
/* We should do some optimisation work here I think. Ok for now though */
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
}
void pcibios_align_resource(void *data, struct resource *res,
resource_size_t size)
{
}
void __init pcibios_update_resource(struct pci_dev *dev, struct resource *root,
struct resource *res, int resource)
{
unsigned long where, size;
u32 reg;
printk("PCI: Assigning %3s %08lx to %s\n",
res->flags & IORESOURCE_IO ? "IO" : "MEM",
res->start, dev->name);
where = PCI_BASE_ADDRESS_0 + resource * 4;
size = res->end - res->start;
pci_read_config_dword(dev, where, &reg);
reg = (reg & size) | (((u32) (res->start - root->start)) & ~size);
pci_write_config_dword(dev, where, reg);
}
void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as certain crappy BIOSes forget to set it properly.
*/
unsigned int pcibios_max_latency = 255;
void pcibios_set_master(struct pci_dev *dev)
{
u8 lat;
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
if (lat < 16)
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
else if (lat > pcibios_max_latency)
lat = pcibios_max_latency;
else
return;
printk("PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

172
arch/sh/boards/overdrive/io.c
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@ -1,172 +0,0 @@
/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* This file contains the I/O routines for use on the overdrive board
*
*/
#include <linux/types.h>
#include <linux/delay.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/overdrive/overdrive.h>
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the SuperH architecture, we just read/write the
* memory location directly.
*/
#define dprintk(x...)
/* Translates an IO address to where it is mapped in memory */
#define io_addr(x) (((unsigned)(x))|PCI_GTIO_BASE)
unsigned char od_inb(unsigned long port)
{
dprintk("od_inb(%x)\n", port);
return readb(io_addr(port)) & 0xff;
}
unsigned short od_inw(unsigned long port)
{
dprintk("od_inw(%x)\n", port);
return readw(io_addr(port)) & 0xffff;
}
unsigned int od_inl(unsigned long port)
{
dprintk("od_inl(%x)\n", port);
return readl(io_addr(port));
}
void od_outb(unsigned char value, unsigned long port)
{
dprintk("od_outb(%x, %x)\n", value, port);
writeb(value, io_addr(port));
}
void od_outw(unsigned short value, unsigned long port)
{
dprintk("od_outw(%x, %x)\n", value, port);
writew(value, io_addr(port));
}
void od_outl(unsigned int value, unsigned long port)
{
dprintk("od_outl(%x, %x)\n", value, port);
writel(value, io_addr(port));
}
/* This is horrible at the moment - needs more work to do something sensible */
#define IO_DELAY() udelay(10)
#define OUT_DELAY(x,type) \
void od_out##x##_p(unsigned type value,unsigned long port){out##x(value,port);IO_DELAY();}
#define IN_DELAY(x,type) \
unsigned type od_in##x##_p(unsigned long port) {unsigned type tmp=in##x(port);IO_DELAY();return tmp;}
OUT_DELAY(b,char)
OUT_DELAY(w,short)
OUT_DELAY(l,int)
IN_DELAY(b,char)
IN_DELAY(w,short)
IN_DELAY(l,int)
/* Now for the string version of these functions */
void od_outsb(unsigned long port, const void *addr, unsigned long count)
{
int i;
unsigned char *p = (unsigned char *) addr;
for (i = 0; i < count; i++, p++) {
outb(*p, port);
}
}
void od_insb(unsigned long port, void *addr, unsigned long count)
{
int i;
unsigned char *p = (unsigned char *) addr;
for (i = 0; i < count; i++, p++) {
*p = inb(port);
}
}
/* For the 16 and 32 bit string functions, we have to worry about alignment.
* The SH does not do unaligned accesses, so we have to read as bytes and
* then write as a word or dword.
* This can be optimised a lot more, especially in the case where the data
* is aligned
*/
void od_outsw(unsigned long port, const void *addr, unsigned long count)
{
int i;
unsigned short tmp;
unsigned char *p = (unsigned char *) addr;
for (i = 0; i < count; i++, p += 2) {
tmp = (*p) | ((*(p + 1)) << 8);
outw(tmp, port);
}
}
void od_insw(unsigned long port, void *addr, unsigned long count)
{
int i;
unsigned short tmp;
unsigned char *p = (unsigned char *) addr;
for (i = 0; i < count; i++, p += 2) {
tmp = inw(port);
p[0] = tmp & 0xff;
p[1] = (tmp >> 8) & 0xff;
}
}
void od_outsl(unsigned long port, const void *addr, unsigned long count)
{
int i;
unsigned tmp;
unsigned char *p = (unsigned char *) addr;
for (i = 0; i < count; i++, p += 4) {
tmp = (*p) | ((*(p + 1)) << 8) | ((*(p + 2)) << 16) |
((*(p + 3)) << 24);
outl(tmp, port);
}
}
void od_insl(unsigned long port, void *addr, unsigned long count)
{
int i;
unsigned tmp;
unsigned char *p = (unsigned char *) addr;
for (i = 0; i < count; i++, p += 4) {
tmp = inl(port);
p[0] = tmp & 0xff;
p[1] = (tmp >> 8) & 0xff;
p[2] = (tmp >> 16) & 0xff;
p[3] = (tmp >> 24) & 0xff;
}
}

191
arch/sh/boards/overdrive/irq.c
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@ -1,191 +0,0 @@
/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Looks after interrupts on the overdrive board.
*
* Bases on the IPR irq system
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/overdrive/overdrive.h>
struct od_data {
int overdrive_irq;
int irq_mask;
};
#define NUM_EXTERNAL_IRQS 16
#define EXTERNAL_IRQ_NOT_IN_USE (-1)
#define EXTERNAL_IRQ_NOT_ASSIGNED (-1)
/*
* This table is used to determine what to program into the FPGA's CT register
* for the specified Linux IRQ.
*
* The irq_mask gives the interrupt number from the PCI board (PCI_Int(6:0))
* but is one greater than that because the because the FPGA treats 0
* as disabled, a value of 1 asserts PCI_Int0, and so on.
*
* The overdrive_irq specifies which of the eight interrupt sources generates
* that interrupt, and but is multiplied by four to give the bit offset into
* the CT register.
*
* The seven interrupts levels (SH4 IRL's) we have available here is hardwired
* by the EPLD. The assignments here of which PCI interrupt generates each
* level is arbitary.
*/
static struct od_data od_data_table[NUM_EXTERNAL_IRQS] = {
/* overdrive_irq , irq_mask */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 0 */
{EXTERNAL_IRQ_NOT_ASSIGNED, 7}, /* 1 */
{EXTERNAL_IRQ_NOT_ASSIGNED, 6}, /* 2 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 3 */
{EXTERNAL_IRQ_NOT_ASSIGNED, 5}, /* 4 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 5 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 6 */
{EXTERNAL_IRQ_NOT_ASSIGNED, 4}, /* 7 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 8 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 9 */
{EXTERNAL_IRQ_NOT_ASSIGNED, 3}, /* 10 */
{EXTERNAL_IRQ_NOT_ASSIGNED, 2}, /* 11 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 12 */
{EXTERNAL_IRQ_NOT_ASSIGNED, 1}, /* 13 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE}, /* 14 */
{EXTERNAL_IRQ_NOT_ASSIGNED, EXTERNAL_IRQ_NOT_IN_USE} /* 15 */
};
static void set_od_data(int overdrive_irq, int irq)
{
if (irq >= NUM_EXTERNAL_IRQS || irq < 0)
return;
od_data_table[irq].overdrive_irq = overdrive_irq << 2;
}
static void enable_od_irq(unsigned int irq);
void disable_od_irq(unsigned int irq);
/* shutdown is same as "disable" */
#define shutdown_od_irq disable_od_irq
static void mask_and_ack_od(unsigned int);
static void end_od_irq(unsigned int irq);
static unsigned int startup_od_irq(unsigned int irq)
{
enable_od_irq(irq);
return 0; /* never anything pending */
}
static struct hw_interrupt_type od_irq_type = {
.typename = "Overdrive-IRQ",
.startup = startup_od_irq,
.shutdown = shutdown_od_irq,
.enable = enable_od_irq,
.disable = disable_od_irq,
.ack = mask_and_ack_od,
.end = end_od_irq
};
static void disable_od_irq(unsigned int irq)
{
unsigned val, flags;
int overdrive_irq;
unsigned mask;
/* Not a valid interrupt */
if (irq < 0 || irq >= NUM_EXTERNAL_IRQS)
return;
/* Is is necessary to use a cli here? Would a spinlock not be
* mroe efficient?
*/
local_irq_save(flags);
overdrive_irq = od_data_table[irq].overdrive_irq;
if (overdrive_irq != EXTERNAL_IRQ_NOT_ASSIGNED) {
mask = ~(0x7 << overdrive_irq);
val = ctrl_inl(OVERDRIVE_INT_CT);
val &= mask;
ctrl_outl(val, OVERDRIVE_INT_CT);
}
local_irq_restore(flags);
}
static void enable_od_irq(unsigned int irq)
{
unsigned val, flags;
int overdrive_irq;
unsigned mask;
/* Not a valid interrupt */
if (irq < 0 || irq >= NUM_EXTERNAL_IRQS)
return;
/* Set priority in OD back to original value */
local_irq_save(flags);
/* This one is not in use currently */
overdrive_irq = od_data_table[irq].overdrive_irq;
if (overdrive_irq != EXTERNAL_IRQ_NOT_ASSIGNED) {
val = ctrl_inl(OVERDRIVE_INT_CT);
mask = ~(0x7 << overdrive_irq);
val &= mask;
mask = od_data_table[irq].irq_mask << overdrive_irq;
val |= mask;
ctrl_outl(val, OVERDRIVE_INT_CT);
}
local_irq_restore(flags);
}
/* this functions sets the desired irq handler to be an overdrive type */
static void __init make_od_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].chip = &od_irq_type;
disable_od_irq(irq);
}
static void mask_and_ack_od(unsigned int irq)
{
disable_od_irq(irq);
}
static void end_od_irq(unsigned int irq)
{
enable_od_irq(irq);
}
void __init init_overdrive_irq(void)
{
int i;
/* Disable all interrupts */
ctrl_outl(0, OVERDRIVE_INT_CT);
/* Update interrupt pin mode to use encoded interrupts */
i = ctrl_inw(INTC_ICR);
i &= ~INTC_ICR_IRLM;
ctrl_outw(i, INTC_ICR);
for (i = 0; i < NUM_EXTERNAL_IRQS; i++) {
if (od_data_table[i].irq_mask != EXTERNAL_IRQ_NOT_IN_USE) {
make_od_irq(i);
} else if (i != 15) { // Cannot use imask on level 15
make_imask_irq(i);
}
}
/* Set up the interrupts */
set_od_data(OVERDRIVE_PCI_INTA, OVERDRIVE_PCI_IRQ1);
set_od_data(OVERDRIVE_PCI_INTB, OVERDRIVE_PCI_IRQ2);
set_od_data(OVERDRIVE_AUDIO_INT, OVERDRIVE_ESS_IRQ);
}

58
arch/sh/boards/overdrive/led.c
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@ -1,58 +0,0 @@
/*
* linux/arch/sh/overdrive/led.c
*
* Copyright (C) 1999 Stuart Menefy <stuart.menefy@st.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* This file contains an Overdrive specific LED feature.
*/
#include <asm/system.h>
#include <asm/io.h>
#include <asm/overdrive/overdrive.h>
static void mach_led(int position, int value)
{
unsigned long flags;
unsigned long reg;
local_irq_save(flags);
reg = readl(OVERDRIVE_CTRL);
if (value) {
reg |= (1<<3);
} else {
reg &= ~(1<<3);
}
writel(reg, OVERDRIVE_CTRL);
local_irq_restore(flags);
}
#ifdef CONFIG_HEARTBEAT
#include <linux/sched.h>
/* acts like an actual heart beat -- ie thump-thump-pause... */
void heartbeat_od(void)
{
static unsigned cnt = 0, period = 0, dist = 0;
if (cnt == 0 || cnt == dist)
mach_led( -1, 1);
else if (cnt == 7 || cnt == dist+7)
mach_led( -1, 0);
if (++cnt > period) {
cnt = 0;
/* The hyperbolic function below modifies the heartbeat period
* length in dependency of the current (5min) load. It goes
* through the points f(0)=126, f(1)=86, f(5)=51,
* f(inf)->30. */
period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
dist = period / 4;
}
}
#endif /* CONFIG_HEARTBEAT */

62
arch/sh/boards/overdrive/mach.c
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/*
* linux/arch/sh/overdrive/mach.c
*
* Copyright (C) 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Machine vector for the STMicroelectronics Overdrive
*/
#include <linux/init.h>
#include <asm/machvec.h>
#include <asm/rtc.h>
#include <asm/machvec_init.h>
#include <asm/io_unknown.h>
#include <asm/io_generic.h>
#include <asm/overdrive/io.h>
void heartbeat_od(void);
void init_overdrive_irq(void);
void galileo_pcibios_init(void);
/*
* The Machine Vector
*/
struct sh_machine_vector mv_od __initmv = {
.mv_nr_irqs = 48,
.mv_inb = od_inb,
.mv_inw = od_inw,
.mv_inl = od_inl,
.mv_outb = od_outb,
.mv_outw = od_outw,
.mv_outl = od_outl,
.mv_inb_p = od_inb_p,
.mv_inw_p = od_inw_p,
.mv_inl_p = od_inl_p,
.mv_outb_p = od_outb_p,
.mv_outw_p = od_outw_p,
.mv_outl_p = od_outl_p,
.mv_insb = od_insb,
.mv_insw = od_insw,
.mv_insl = od_insl,
.mv_outsb = od_outsb,
.mv_outsw = od_outsw,
.mv_outsl = od_outsl,
#ifdef CONFIG_PCI
.mv_init_irq = init_overdrive_irq,
#endif
#ifdef CONFIG_HEARTBEAT
.mv_heartbeat = heartbeat_od,
#endif
};
ALIAS_MV(od)

46
arch/sh/boards/overdrive/pcidma.c
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@ -1,46 +0,0 @@
/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Dynamic DMA mapping support.
*
* On the overdrive, we can only DMA from memory behind the PCI bus!
* this means that all DMA'able memory must come from there.
* this restriction will not apply to later boards.
*/
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <asm/io.h>
void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t * dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC;
printk("BUG: pci_alloc_consistent() called - not yet supported\n");
/* We ALWAYS need DMA memory on the overdrive hardware,
* due to it's extreme weirdness
* Need to flush the cache here as well, since the memory
* can still be seen through the cache!
*/
gfp |= GFP_DMA;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
*dma_handle = virt_to_bus(ret);
}
return ret;
}
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages((unsigned long) vaddr, get_order(size));
}

36
arch/sh/boards/overdrive/setup.c
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@ -1,36 +0,0 @@
/*
* arch/sh/overdrive/setup.c
*
* Copyright (C) 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* STMicroelectronics Overdrive Support.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/overdrive/overdrive.h>
#include <asm/overdrive/fpga.h>
const char *get_system_type(void)
{
return "SH7750 Overdrive";
}
/*
* Initialize the board
*/
int __init platform_setup(void)
{
#ifdef CONFIG_PCI
init_overdrive_fpga();
galileo_init();
#endif
/* Enable RS232 receive buffers */
writel(0x1e, OVERDRIVE_CTRL);
}

6
arch/sh/boards/sh2000/Makefile
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@ -1,6 +0,0 @@
#
# Makefile for the SH2000 specific parts of the kernel
#
obj-y := setup.o

70
arch/sh/boards/sh2000/setup.c
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@ -1,70 +0,0 @@
/*
* linux/arch/sh/kernel/setup_sh2000.c
*
* Copyright (C) 2001 SUGIOKA Tochinobu
*
* SH-2000 Support.
*
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/machvec.h>
#include <asm/mach/sh2000.h>
#define CF_CIS_BASE 0xb4200000
#define PORT_PECR 0xa4000108
#define PORT_PHCR 0xa400010E
#define PORT_ICR1 0xa4000010
#define PORT_IRR0 0xa4000004
#define IDE_OFFSET 0xb6200000
#define NIC_OFFSET 0xb6000000
#define EXTBUS_OFFSET 0xba000000
const char *get_system_type(void)
{
return "sh2000";
}
static unsigned long sh2000_isa_port2addr(unsigned long offset)
{
if((offset & ~7) == 0x1f0 || offset == 0x3f6)
return IDE_OFFSET + offset;
else if((offset & ~0x1f) == 0x300)
return NIC_OFFSET + offset;
return EXTBUS_OFFSET + offset;
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_sh2000 __initmv = {
.mv_nr_irqs = 80,
.mv_isa_port2addr = sh2000_isa_port2addr,
};
ALIAS_MV(sh2000)
/*
* Initialize the board
*/
int __init platform_setup(void)
{
/* XXX: RTC setting comes here */
/* These should be done by BIOS/IPL ... */
/* Enable nCE2A, nCE2B output */
ctrl_outw(ctrl_inw(PORT_PECR) & ~0xf00, PORT_PECR);
/* Enable the Compact Flash card, and set the level interrupt */
ctrl_outw(0x0042, CF_CIS_BASE+0x0200);
/* Enable interrupt */
ctrl_outw(ctrl_inw(PORT_PHCR) & ~0x03f3, PORT_PHCR);
ctrl_outw(1, PORT_ICR1);
ctrl_outw(ctrl_inw(PORT_IRR0) & ~0xff3f, PORT_IRR0);
printk(KERN_INFO "SH-2000 Setup...done\n");
return 0;
}

2
arch/sh/tools/mach-types
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@ -13,11 +13,9 @@ SE SH_SOLUTION_ENGINE
HP6XX SH_HP6XX
HD64461 HD64461
HD64465 HD64465
SH2000 SH_SH2000
SATURN SH_SATURN
DREAMCAST SH_DREAMCAST
BIGSUR SH_BIGSUR
ADX SH_ADX
MPC1211 SH_MPC1211
SNAPGEAR SH_SECUREEDGE5410
HS7751RVOIP SH_HS7751RVOIP

86
include/asm-sh/adx/io.h
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@ -1,86 +0,0 @@
/*
* include/asm-sh/io_adx.h
*
* Copyright (C) 2001 A&D Co., Ltd.
*
* This file may be copied or modified under the terms of the GNU
* General Public License. See linux/COPYING for more information.
*
* IO functions for an A&D ADX Board
*/
#ifndef _ASM_SH_IO_ADX_H
#define _ASM_SH_IO_ADX_H
#include <asm/io_generic.h>
extern unsigned char adx_inb(unsigned long port);
extern unsigned short adx_inw(unsigned long port);
extern unsigned int adx_inl(unsigned long port);
extern void adx_outb(unsigned char value, unsigned long port);
extern void adx_outw(unsigned short value, unsigned long port);
extern void adx_outl(unsigned int value, unsigned long port);
extern unsigned char adx_inb_p(unsigned long port);
extern void adx_outb_p(unsigned char value, unsigned long port);
extern void adx_insb(unsigned long port, void *addr, unsigned long count);
extern void adx_insw(unsigned long port, void *addr, unsigned long count);
extern void adx_insl(unsigned long port, void *addr, unsigned long count);
extern void adx_outsb(unsigned long port, const void *addr, unsigned long count);
extern void adx_outsw(unsigned long port, const void *addr, unsigned long count);
extern void adx_outsl(unsigned long port, const void *addr, unsigned long count);
extern unsigned char adx_readb(unsigned long addr);
extern unsigned short adx_readw(unsigned long addr);
extern unsigned int adx_readl(unsigned long addr);
extern void adx_writeb(unsigned char b, unsigned long addr);
extern void adx_writew(unsigned short b, unsigned long addr);
extern void adx_writel(unsigned int b, unsigned long addr);
extern void * adx_ioremap(unsigned long offset, unsigned long size);
extern void adx_iounmap(void *addr);
extern unsigned long adx_isa_port2addr(unsigned long offset);
extern void setup_adx(void);
extern void init_adx_IRQ(void);
#ifdef __WANT_IO_DEF
#define __inb adx_inb
#define __inw adx_inw
#define __inl adx_inl
#define __outb adx_outb
#define __outw adx_outw
#define __outl adx_outl
#define __inb_p adx_inb_p
#define __inw_p adx_inw
#define __inl_p adx_inl
#define __outb_p adx_outb_p
#define __outw_p adx_outw
#define __outl_p adx_outl
#define __insb adx_insb
#define __insw adx_insw
#define __insl adx_insl
#define __outsb adx_outsb
#define __outsw adx_outsw
#define __outsl adx_outsl
#define __readb adx_readb
#define __readw adx_readw
#define __readl adx_readl
#define __writeb adx_writeb
#define __writew adx_writew
#define __writel adx_writel
#define __isa_port2addr adx_isa_port2addr
#define __ioremap adx_ioremap
#define __iounmap adx_iounmap
#endif
#endif /* _ASM_SH_IO_AANDD_H */

22
include/asm-sh/cat68701/io.h
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@ -1,22 +0,0 @@
/*
* include/asm-sh/io_cat68701.h
*
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
* 2001 Yutarou Ebihar (ebihara@si-linux.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an AONE Corp. CAT-68701 SH7708 Borad
*/
#ifndef _ASM_SH_IO_CAT68701_H
#define _ASM_SH_IO_CAT68701_H
extern unsigned long cat68701_isa_port2addr(unsigned long offset);
extern int cat68701_irq_demux(int irq);
extern void init_cat68701_IRQ(void);
extern void heartbeat_cat68701(void);
#endif /* _ASM_SH_IO_CAT68701_H */

27
include/asm-sh/cqreek/cqreek.h
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@ -1,27 +0,0 @@
#ifndef __ASM_SH_CQREEK_CQREEK_H
#define __ASM_SH_CQREEK_CQREEK_H
#define BRIDGE_FEATURE 0x0002
#define BRIDGE_IDE_CTRL 0x0018
#define BRIDGE_IDE_INTR_LVL 0x001A
#define BRIDGE_IDE_INTR_MASK 0x001C
#define BRIDGE_IDE_INTR_STAT 0x001E
#define BRIDGE_ISA_CTRL 0x0028
#define BRIDGE_ISA_INTR_LVL 0x002A
#define BRIDGE_ISA_INTR_MASK 0x002C
#define BRIDGE_ISA_INTR_STAT 0x002E
/* arch/sh/boards/cqreek/setup.c */
extern void setup_cqreek(void);
/* arch/sh/boards/cqreek/irq.c */
extern int cqreek_has_ide, cqreek_has_isa;
extern void init_cqreek_IRQ(void);
/* arch/sh/boards/cqreek/io.c */
extern unsigned long cqreek_port2addr(unsigned long port);
#endif /* __ASM_SH_CQREEK_CQREEK_H */

10
include/asm-sh/dmida/io.h
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@ -1,10 +0,0 @@
#ifndef __ASM_SH_DMIDA_IO_H
#define __ASM_SH_DMIDA_IO_H
/*
* Nothing special here.. just use the generic cchip io routines.
*/
#include <asm/hd64465/io.h>
#endif /* __ASM_SH_DMIDA_IO_H */

43
include/asm-sh/harp/harp.h
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@ -1,43 +0,0 @@
/*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Defintions applicable to the STMicroelectronics ST40STB1 HARP and
* compatible boards.
*/
#if defined(CONFIG_SH_STB1_HARP)
#define EPLD_BASE 0xa0800000
#define EPLD_LED (EPLD_BASE+0x000c0000)
#define EPLD_INTSTAT0 (EPLD_BASE+0x00200000)
#define EPLD_INTSTAT1 (EPLD_BASE+0x00240000)
#define EPLD_INTMASK0 (EPLD_BASE+0x00280000)
#define EPLD_INTMASK1 (EPLD_BASE+0x002c0000)
#define EPLD_PAGEADDR (EPLD_BASE+0x00300000)
#define EPLD_REVID1 (EPLD_BASE+0x00380000)
#define EPLD_REVID2 (EPLD_BASE+0x003c0000)
#define EPLD_LED_ON 1
#define EPLD_LED_OFF 0
#elif defined(CONFIG_SH_STB1_OVERDRIVE)
#define EPLD_BASE 0xa7000000
#define EPLD_REVID (EPLD_BASE+0x00000000)
#define EPLD_LED (EPLD_BASE+0x00040000)
#define EPLD_INTMASK0 (EPLD_BASE+0x001c0000)
#define EPLD_INTMASK1 (EPLD_BASE+0x00200000)
#define EPLD_INTSTAT0 (EPLD_BASE+0x00240000)
#define EPLD_INTSTAT1 (EPLD_BASE+0x00280000)
#define EPLD_LED_ON 0
#define EPLD_LED_OFF 1
#else
#error Unknown board
#endif

10
include/asm-sh/harp/io.h
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@ -1,10 +0,0 @@
#ifndef __ASM_SH_HARP_IO_H
#define __ASM_SH_HARP_IO_H
/*
* Nothing special here.. just use the generic cchip io routines.
*/
#include <asm/hd64465/io.h>
#endif /* __ASM_SH_HARP_IO_H */

15
include/asm-sh/overdrive/fpga.h
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@ -1,15 +0,0 @@
/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#ifndef __FPGA_OD_H__
#define __FPGA_OD_H__
/* This routine will program up the fpga which interfaces to the galileo */
int init_overdrive_fpga(void);
#endif

109
include/asm-sh/overdrive/gt64111.h
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@ -1,109 +0,0 @@
#ifndef _GT64111_H_
#define _GT64111_H_
#define MASTER_INTERFACE 0x0
#define RAS10_LO_DEC_ADR 0x8
#define RAS10_HI_DEC_ADR 0x10
#define RAS32_LO_DEC_ADR 0x18
#define RAS32_HI_DEC_ADR 0x20
#define CS20_LO_DEC_ADR 0x28
#define CS20_HI_DEC_ADR 0x30
#define CS3_LO_DEC_ADR 0x38
#define CS3_HI_DEC_ADR 0x40
#define PCI_IO_LO_DEC_ADR 0x48
#define PCI_IO_HI_DEC_ADR 0x50
#define PCI_MEM0_LO_DEC_ADR 0x58
#define PCI_MEM0_HI_DEC_ADR 0x60
#define INTERNAL_SPACE_DEC 0x68
#define BUS_ERR_ADR_LO_CPU 0x70
#define READONLY0 0x78
#define PCI_MEM1_LO_DEC_ADR 0x80
#define PCI_MEM1_HI_DEC_ADR 0x88
#define RAS0_LO_DEC_ADR 0x400
#define RAS0_HI_DEC_ADR 0x404
#define RAS1_LO_DEC_ADR 0x408
#define RAS1_HI_DEC_ADR 0x40c
#define RAS2_LO_DEC_ADR 0x410
#define RAS2_HI_DEC_ADR 0x414
#define RAS3_LO_DEC_ADR 0x418
#define RAS3_HI_DEC_ADR 0x41c
#define DEV_CS0_LO_DEC_ADR 0x420
#define DEV_CS0_HI_DEC_ADR 0x424
#define DEV_CS1_LO_DEC_ADR 0x428
#define DEV_CS1_HI_DEC_ADR 0x42c
#define DEV_CS2_LO_DEC_ADR 0x430
#define DEV_CS2_HI_DEC_ADR 0x434
#define DEV_CS3_LO_DEC_ADR 0x438
#define DEV_CS3_HI_DEC_ADR 0x43c
#define DEV_BOOTCS_LO_DEC_ADR 0x440
#define DEV_BOOTCS_HI_DEC_ADR 0x444
#define DEV_ADR_DEC_ERR 0x470
#define DRAM_CFG 0x448
#define DRAM_BANK0_PARMS 0x44c
#define DRAM_BANK1_PARMS 0x450
#define DRAM_BANK2_PARMS 0x454
#define DRAM_BANK3_PARMS 0x458
#define DEV_BANK0_PARMS 0x45c
#define DEV_BANK1_PARMS 0x460
#define DEV_BANK2_PARMS 0x464
#define DEV_BANK3_PARMS 0x468
#define DEV_BOOT_BANK_PARMS 0x46c
#define CH0_DMA_BYTECOUNT 0x800
#define CH1_DMA_BYTECOUNT 0x804
#define CH2_DMA_BYTECOUNT 0x808
#define CH3_DMA_BYTECOUNT 0x80c
#define CH0_DMA_SRC_ADR 0x810
#define CH1_DMA_SRC_ADR 0x814
#define CH2_DMA_SRC_ADR 0x818
#define CH3_DMA_SRC_ADR 0x81c
#define CH0_DMA_DST_ADR 0x820
#define CH1_DMA_DST_ADR 0x824
#define CH2_DMA_DST_ADR 0x828
#define CH3_DMA_DST_ADR 0x82c
#define CH0_NEXT_REC_PTR 0x830
#define CH1_NEXT_REC_PTR 0x834
#define CH2_NEXT_REC_PTR 0x838
#define CH3_NEXT_REC_PTR 0x83c
#define CH0_CTRL 0x840
#define CH1_CTRL 0x844
#define CH2_CTRL 0x848
#define CH3_CTRL 0x84c
#define DMA_ARBITER 0x860
#define TIMER0 0x850
#define TIMER1 0x854
#define TIMER2 0x858
#define TIMER3 0x85c
#define TIMER_CTRL 0x864
#define PCI_CMD 0xc00
#define PCI_TIMEOUT 0xc04
#define PCI_RAS10_BANK_SIZE 0xc08
#define PCI_RAS32_BANK_SIZE 0xc0c
#define PCI_CS20_BANK_SIZE 0xc10
#define PCI_CS3_BANK_SIZE 0xc14
#define PCI_SERRMASK 0xc28
#define PCI_INTACK 0xc34
#define PCI_BAR_EN 0xc3c
#define PCI_CFG_ADR 0xcf8
#define PCI_CFG_DATA 0xcfc
#define PCI_INTCAUSE 0xc18
#define PCI_MAST_MASK 0xc1c
#define PCI_PCIMASK 0xc24
#define BAR_ENABLE_ADR 0xc3c
/* These are config registers, accessible via PCI space */
#define PCI_CONFIG_RAS10_BASE_ADR 0x010
#define PCI_CONFIG_RAS32_BASE_ADR 0x014
#define PCI_CONFIG_CS20_BASE_ADR 0x018
#define PCI_CONFIG_CS3_BASE_ADR 0x01c
#define PCI_CONFIG_INT_REG_MM_ADR 0x020
#define PCI_CONFIG_INT_REG_IO_ADR 0x024
#define PCI_CONFIG_BOARD_VENDOR 0x02c
#define PCI_CONFIG_ROM_ADR 0x030
#define PCI_CONFIG_INT_PIN_LINE 0x03c
#endif

39
include/asm-sh/overdrive/io.h
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@ -1,39 +0,0 @@
/*
* include/asm-sh/io_od.h
*
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an STMicroelectronics Overdrive
*/
#ifndef _ASM_SH_IO_OD_H
#define _ASM_SH_IO_OD_H
extern unsigned char od_inb(unsigned long port);
extern unsigned short od_inw(unsigned long port);
extern unsigned int od_inl(unsigned long port);
extern void od_outb(unsigned char value, unsigned long port);
extern void od_outw(unsigned short value, unsigned long port);
extern void od_outl(unsigned int value, unsigned long port);
extern unsigned char od_inb_p(unsigned long port);
extern unsigned short od_inw_p(unsigned long port);
extern unsigned int od_inl_p(unsigned long port);
extern void od_outb_p(unsigned char value, unsigned long port);
extern void od_outw_p(unsigned short value, unsigned long port);
extern void od_outl_p(unsigned int value, unsigned long port);
extern void od_insb(unsigned long port, void *addr, unsigned long count);
extern void od_insw(unsigned long port, void *addr, unsigned long count);
extern void od_insl(unsigned long port, void *addr, unsigned long count);
extern void od_outsb(unsigned long port, const void *addr, unsigned long count);
extern void od_outsw(unsigned long port, const void *addr, unsigned long count);
extern void od_outsl(unsigned long port, const void *addr, unsigned long count);
extern unsigned long od_isa_port2addr(unsigned long offset);
#endif /* _ASM_SH_IO_OD_H */

88
include/asm-sh/overdrive/overdrive.h
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@ -1,88 +0,0 @@
/*
* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#ifndef __OVERDRIVE_H__
#define __OVERDRIVE_H__
#define OVERDRIVE_INT_CT 0xa3a00000
#define OVERDRIVE_INT_DT 0xa3b00000
#define OVERDRIVE_CTRL 0xa3000000
/* Shoving all these bits into the same register is not a good idea.
* As soon as I get a spare moment, I'll change the FPGA and put each
* bit in a separate register
*/
#define VALID_CTRL_BITS 0x1f
#define ENABLE_RS232_MASK 0x1e
#define DISABLE_RS232_BIT 0x01
#define ENABLE_NMI_MASK 0x1d
#define DISABLE_NMI_BIT 0x02
#define RESET_PCI_MASK 0x1b
#define ENABLE_PCI_BIT 0x04
#define ENABLE_LED_MASK 0x17
#define DISABLE_LED_BIT 0x08
#define RESET_FPGA_MASK 0x0f
#define ENABLE_FPGA_BIT 0x10
#define FPGA_DCLK_ADDRESS 0xA3C00000
#define FPGA_DATA 0x01 /* W */
#define FPGA_CONFDONE 0x02 /* R */
#define FPGA_NOT_STATUS 0x04 /* R */
#define FPGA_INITDONE 0x08 /* R */
#define FPGA_TIMEOUT 100000
/* Interrupts for the overdrive. Note that these numbers have
* nothing to do with the actual IRQ numbers they appear on,
* this is all programmable. This is simply the position in the
* INT_CT register.
*/
#define OVERDRIVE_PCI_INTA 0
#define OVERDRIVE_PCI_INTB 1
#define OVERDRIVE_PCI_INTC 2
#define OVERDRIVE_PCI_INTD 3
#define OVERDRIVE_GALILEO_INT 4
#define OVERDRIVE_GALILEO_LOCAL_INT 5
#define OVERDRIVE_AUDIO_INT 6
#define OVERDRIVE_KEYBOARD_INT 7
/* Which Linux IRQ should we assign to each interrupt source? */
#define OVERDRIVE_PCI_IRQ1 2
#ifdef CONFIG_HACKED_NE2K
#define OVERDRIVE_PCI_IRQ2 7
#else
#define OVERDRIVE_PCI_IRQ2 2
#undef OVERDRIVE_PCI_INTB
#define OVERDRIVE_PCI_INTB OVERDRIVE_PCI_INTA
#endif
/* Put the ESS solo audio chip on IRQ 4 */
#define OVERDRIVE_ESS_IRQ 4
/* Where the memory behind the PCI bus appears */
#define PCI_DRAM_BASE 0xb7000000
#define PCI_DRAM_SIZE (16*1024*1024)
#define PCI_DRAM_FINISH (PCI_DRAM_BASE+PCI_DRAM_SIZE-1)
/* Where the IO region appears in the memory */
#define PCI_GTIO_BASE 0xb8000000
#endif

8
include/asm-sh/sh2000/sh2000.h
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@ -1,8 +0,0 @@
#ifndef __ASM_SH_SH2000_SH2000_H
#define __ASM_SH_SH2000_SH2000_H
/* arch/sh/boards/sh2000/setup.c */
extern int setup_sh2000(void);
#endif /* __ASM_SH_SH2000_SH2000_H */