x86, numaq: consolidate code
Move all the NUMAQ subarch definitions into numaq.c. With this it ceases to depend on build-time subarch features. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
Родитель
328386d7ab
Коммит
5a44632f77
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@ -1,122 +0,0 @@
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#ifndef __ASM_NUMAQ_APIC_H
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#define __ASM_NUMAQ_APIC_H
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#include <asm/io.h>
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#include <linux/mmzone.h>
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#include <linux/nodemask.h>
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#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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static inline const cpumask_t *numaq_target_cpus(void)
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{
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return &CPU_MASK_ALL;
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}
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static inline unsigned long
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numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return physid_isset(apicid, bitmap);
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}
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static inline unsigned long numaq_check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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#define apicid_cluster(apicid) (apicid & 0xF0)
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static inline int numaq_apic_id_registered(void)
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{
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return 1;
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}
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static inline void numaq_init_apic_ldr(void)
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{
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/* Already done in NUMA-Q firmware */
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}
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static inline void numaq_setup_apic_routing(void)
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{
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"NUMA-Q", nr_ioapics);
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}
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/*
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* Skip adding the timer int on secondary nodes, which causes
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* a small but painful rift in the time-space continuum.
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*/
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static inline int numaq_multi_timer_check(int apic, int irq)
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{
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return apic != 0 && irq == 0;
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}
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static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map)
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{
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/* We don't have a good way to do this yet - hack */
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return physids_promote(0xFUL);
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}
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/* Mapping from cpu number to logical apicid */
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extern u8 cpu_2_logical_apicid[];
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static inline int numaq_cpu_to_logical_apicid(int cpu)
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{
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if (cpu >= nr_cpu_ids)
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return BAD_APICID;
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return (int)cpu_2_logical_apicid[cpu];
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}
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/*
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* Supporting over 60 cpus on NUMA-Q requires a locality-dependent
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* cpu to APIC ID relation to properly interact with the intelligent
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* mode of the cluster controller.
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*/
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static inline int numaq_cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < 60)
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return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
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else
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return BAD_APICID;
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}
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static inline int numaq_apicid_to_node(int logical_apicid)
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{
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return logical_apicid >> 4;
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}
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static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid)
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{
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int node = numaq_apicid_to_node(logical_apicid);
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int cpu = __ffs(logical_apicid & 0xf);
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return physid_mask_of_physid(cpu + 4*node);
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}
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extern void *xquad_portio;
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static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return 1;
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}
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/*
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* We use physical apicids here, not logical, so just return the default
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* physical broadcast to stop people from breaking us
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*/
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static inline unsigned int numaq_cpu_mask_to_apicid(const cpumask_t *cpumask)
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{
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return 0x0F;
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}
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static inline unsigned int
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numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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return 0x0F;
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}
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/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
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static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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#endif /* __ASM_NUMAQ_APIC_H */
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@ -1,9 +0,0 @@
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#ifndef __ASM_NUMAQ_APICDEF_H
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#define __ASM_NUMAQ_APICDEF_H
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static inline unsigned int numaq_get_apic_id(unsigned long x)
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{
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return (x >> 24) & 0x0F;
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}
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#endif
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@ -1,22 +0,0 @@
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#ifndef __ASM_NUMAQ_IPI_H
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#define __ASM_NUMAQ_IPI_H
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void default_send_IPI_mask_sequence(const struct cpumask *mask, int vector);
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void default_send_IPI_mask_allbutself(const struct cpumask *mask, int vector);
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static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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default_send_IPI_mask_sequence(mask, vector);
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}
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static inline void numaq_send_IPI_allbutself(int vector)
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{
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default_send_IPI_mask_allbutself(cpu_online_mask, vector);
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}
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static inline void numaq_send_IPI_all(int vector)
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{
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numaq_send_IPI_mask(cpu_online_mask, vector);
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}
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#endif /* __ASM_NUMAQ_IPI_H */
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@ -1,6 +0,0 @@
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#ifndef __ASM_NUMAQ_MPPARSE_H
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#define __ASM_NUMAQ_MPPARSE_H
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extern void numaq_mps_oem_check(struct mpc_table *, char *, char *);
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#endif /* __ASM_NUMAQ_MPPARSE_H */
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@ -1,28 +0,0 @@
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#ifndef __ASM_NUMAQ_WAKECPU_H
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#define __ASM_NUMAQ_WAKECPU_H
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/* This file copes with machines that wakeup secondary CPUs by NMIs */
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#define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8)
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#define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa)
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/*
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* Because we use NMIs rather than the INIT-STARTUP sequence to
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* bootstrap the CPUs, the APIC may be in a weird state. Kick it:
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*/
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static inline void numaq_smp_callin_clear_local_apic(void)
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{
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clear_local_APIC();
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}
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static inline void
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numaq_store_NMI_vector(unsigned short *high, unsigned short *low)
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{
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printk("Storing NMI vector\n");
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*high =
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*((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_HIGH));
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*low =
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*((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_LOW));
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}
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#endif /* __ASM_NUMAQ_WAKECPU_H */
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@ -11,14 +11,175 @@
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <asm/numaq/apicdef.h>
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#include <linux/numa.h>
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#include <linux/smp.h>
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#include <asm/numaq/apic.h>
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#include <asm/numaq/ipi.h>
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#include <asm/numaq/mpparse.h>
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#include <asm/numaq/wakecpu.h>
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#include <asm/numaq.h>
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#include <asm/io.h>
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#include <linux/mmzone.h>
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#include <linux/nodemask.h>
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#define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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static inline unsigned int numaq_get_apic_id(unsigned long x)
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{
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return (x >> 24) & 0x0F;
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}
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void default_send_IPI_mask_sequence(const struct cpumask *mask, int vector);
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void default_send_IPI_mask_allbutself(const struct cpumask *mask, int vector);
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static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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default_send_IPI_mask_sequence(mask, vector);
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}
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static inline void numaq_send_IPI_allbutself(int vector)
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{
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default_send_IPI_mask_allbutself(cpu_online_mask, vector);
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}
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static inline void numaq_send_IPI_all(int vector)
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{
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numaq_send_IPI_mask(cpu_online_mask, vector);
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}
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extern void numaq_mps_oem_check(struct mpc_table *, char *, char *);
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#define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8)
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#define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa)
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/*
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* Because we use NMIs rather than the INIT-STARTUP sequence to
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* bootstrap the CPUs, the APIC may be in a weird state. Kick it:
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*/
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static inline void numaq_smp_callin_clear_local_apic(void)
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{
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clear_local_APIC();
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}
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static inline void
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numaq_store_NMI_vector(unsigned short *high, unsigned short *low)
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{
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printk("Storing NMI vector\n");
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*high =
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*((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_HIGH));
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*low =
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*((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_LOW));
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}
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static inline const cpumask_t *numaq_target_cpus(void)
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{
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return &CPU_MASK_ALL;
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}
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static inline unsigned long
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numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return physid_isset(apicid, bitmap);
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}
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static inline unsigned long numaq_check_apicid_present(int bit)
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{
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return physid_isset(bit, phys_cpu_present_map);
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}
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#define apicid_cluster(apicid) (apicid & 0xF0)
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static inline int numaq_apic_id_registered(void)
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{
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return 1;
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}
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static inline void numaq_init_apic_ldr(void)
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{
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/* Already done in NUMA-Q firmware */
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}
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static inline void numaq_setup_apic_routing(void)
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{
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"NUMA-Q", nr_ioapics);
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}
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/*
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* Skip adding the timer int on secondary nodes, which causes
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* a small but painful rift in the time-space continuum.
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*/
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static inline int numaq_multi_timer_check(int apic, int irq)
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{
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return apic != 0 && irq == 0;
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}
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static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map)
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{
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/* We don't have a good way to do this yet - hack */
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return physids_promote(0xFUL);
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}
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/* Mapping from cpu number to logical apicid */
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extern u8 cpu_2_logical_apicid[];
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static inline int numaq_cpu_to_logical_apicid(int cpu)
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{
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if (cpu >= nr_cpu_ids)
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return BAD_APICID;
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return (int)cpu_2_logical_apicid[cpu];
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}
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/*
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* Supporting over 60 cpus on NUMA-Q requires a locality-dependent
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* cpu to APIC ID relation to properly interact with the intelligent
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* mode of the cluster controller.
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*/
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static inline int numaq_cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < 60)
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return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
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else
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return BAD_APICID;
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}
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static inline int numaq_apicid_to_node(int logical_apicid)
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{
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return logical_apicid >> 4;
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}
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static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid)
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{
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int node = numaq_apicid_to_node(logical_apicid);
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int cpu = __ffs(logical_apicid & 0xf);
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return physid_mask_of_physid(cpu + 4*node);
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}
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extern void *xquad_portio;
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static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return 1;
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}
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/*
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* We use physical apicids here, not logical, so just return the default
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* physical broadcast to stop people from breaking us
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*/
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static inline unsigned int numaq_cpu_mask_to_apicid(const cpumask_t *cpumask)
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{
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return 0x0F;
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}
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static inline unsigned int
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numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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return 0x0F;
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}
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/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
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static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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static int __numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
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{
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numaq_mps_oem_check(mpc, oem, productid);
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@ -5,7 +5,7 @@
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/nodemask.h>
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#include <mach_apic.h>
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#include <asm/genapic.h>
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#include <asm/mpspec.h>
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#include <asm/pci_x86.h>
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