ARM: dts: r8a7742: Add CAN support
Add the definitions for can0 and can1 to the r8a7742 SoC dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200816190732.6905-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -36,6 +36,14 @@
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clock-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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/* External CAN clock */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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cpus {
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cpus {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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@ -951,6 +959,32 @@
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status = "disabled";
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status = "disabled";
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};
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};
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can0: can@e6e80000 {
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compatible = "renesas,can-r8a7742",
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"renesas,rcar-gen2-can";
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reg = <0 0xe6e80000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 916>,
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<&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 916>;
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status = "disabled";
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};
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can1: can@e6e88000 {
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compatible = "renesas,can-r8a7742",
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"renesas,rcar-gen2-can";
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reg = <0 0xe6e88000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 915>,
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<&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 915>;
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status = "disabled";
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};
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pwm0: pwm@e6e30000 {
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pwm0: pwm@e6e30000 {
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compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
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compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
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reg = <0 0xe6e30000 0 0x8>;
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reg = <0 0xe6e30000 0 0x8>;
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