Merge branch 'i2c-for-ben' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into i2c-next
This commit is contained in:
Ben Dooks
Коммит
5a93f42017
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@ -2321,7 +2321,7 @@ static struct clk i2c2_fck = {
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};
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static struct clk i2chs2_fck = {
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.name = "i2chs_fck",
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.name = "i2c_fck",
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.id = 2,
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.parent = &func_96m_ck,
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.flags = CLOCK_IN_OMAP243X,
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@ -2354,7 +2354,7 @@ static struct clk i2c1_fck = {
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};
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static struct clk i2chs1_fck = {
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.name = "i2chs_fck",
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.name = "i2c_fck",
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.id = 1,
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.parent = &func_96m_ck,
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.flags = CLOCK_IN_OMAP243X,
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@ -2,13 +2,16 @@
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* TI OMAP I2C master mode driver
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*
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* Copyright (C) 2003 MontaVista Software, Inc.
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* Copyright (C) 2004 Texas Instruments.
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*
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* Updated to work with multiple I2C interfaces on 24xx by
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* Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
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* Copyright (C) 2005 Nokia Corporation
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* Copyright (C) 2004 - 2007 Texas Instruments.
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*
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* Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
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* Originally written by MontaVista Software, Inc.
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* Additional contributions by:
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* Tony Lindgren <tony@atomide.com>
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* Imre Deak <imre.deak@nokia.com>
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* Juha Yrjölä <juha.yrjola@solidboot.com>
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* Syed Khasim <x0khasim@ti.com>
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* Nishant Menon <nm@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -33,8 +36,14 @@
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#include <linux/completion.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/io.h>
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/* I2C controller revisions */
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#define OMAP_I2C_REV_2 0x20
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/* I2C controller revisions present on specific hardware */
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#define OMAP_I2C_REV_ON_2430 0x36
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#define OMAP_I2C_REV_ON_3430 0x3C
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/* timeout waiting for the controller to respond */
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#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
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@ -43,6 +52,8 @@
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#define OMAP_I2C_IE_REG 0x04
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#define OMAP_I2C_STAT_REG 0x08
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#define OMAP_I2C_IV_REG 0x0c
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/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
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#define OMAP_I2C_WE_REG 0x0c
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#define OMAP_I2C_SYSS_REG 0x10
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#define OMAP_I2C_BUF_REG 0x14
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#define OMAP_I2C_CNT_REG 0x18
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@ -55,8 +66,11 @@
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#define OMAP_I2C_SCLL_REG 0x34
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#define OMAP_I2C_SCLH_REG 0x38
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#define OMAP_I2C_SYSTEST_REG 0x3c
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#define OMAP_I2C_BUFSTAT_REG 0x40
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/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
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#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
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#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
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#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
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#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
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#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
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@ -64,7 +78,8 @@
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#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
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/* I2C Status Register (OMAP_I2C_STAT): */
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#define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */
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#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
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#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
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#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
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#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
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#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
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@ -76,13 +91,34 @@
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#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
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#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
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/* I2C WE wakeup enable register */
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#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
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#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
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#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
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#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
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#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
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#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
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#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
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#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
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#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
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#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
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#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
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OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
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OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
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OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
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OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
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/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
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#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
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#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
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#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
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#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
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/* I2C Configuration Register (OMAP_I2C_CON): */
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#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
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#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
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#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
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#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
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#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
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#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
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@ -91,6 +127,10 @@
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#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
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#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
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/* I2C SCL time value when Master */
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#define OMAP_I2C_SCLL_HSSCLL 8
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#define OMAP_I2C_SCLH_HSSCLH 8
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/* I2C System Test Register (OMAP_I2C_SYSTEST): */
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#ifdef DEBUG
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#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
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@ -103,17 +143,19 @@
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#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
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#endif
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/* I2C System Status register (OMAP_I2C_SYSS): */
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#define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
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/* OCP_SYSSTATUS bit definitions */
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#define SYSS_RESETDONE_MASK (1 << 0)
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/* I2C System Configuration Register (OMAP_I2C_SYSC): */
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#define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
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/* OCP_SYSCONFIG bit definitions */
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#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
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#define SYSC_SIDLEMODE_MASK (0x3 << 3)
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#define SYSC_ENAWAKEUP_MASK (1 << 2)
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#define SYSC_SOFTRESET_MASK (1 << 1)
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#define SYSC_AUTOIDLE_MASK (1 << 0)
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#define SYSC_IDLEMODE_SMART 0x2
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#define SYSC_CLOCKACTIVITY_FCLK 0x2
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/* REVISIT: Use platform_data instead of module parameters */
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/* Fast Mode = 400 kHz, Standard = 100 kHz */
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static int clock = 100; /* Default: 100 kHz */
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module_param(clock, int, 0);
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MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
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struct omap_i2c_dev {
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struct device *dev;
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@ -123,11 +165,17 @@ struct omap_i2c_dev {
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struct clk *fclk; /* Functional clock */
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struct completion cmd_complete;
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struct resource *ioarea;
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u32 speed; /* Speed of bus in Khz */
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u16 cmd_err;
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u8 *buf;
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size_t buf_len;
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struct i2c_adapter adapter;
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unsigned rev1:1;
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u8 fifo_size; /* use as flag and value
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* fifo_size==0 implies no fifo
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* if set, should be trsh+1
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*/
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u8 rev;
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unsigned b_hw:1; /* bad h/w fixes */
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unsigned idle:1;
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u16 iestate; /* Saved interrupt register */
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};
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@ -143,9 +191,9 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
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return __raw_readw(i2c_dev->base + reg);
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}
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static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
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static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
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{
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if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
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if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
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dev->iclk = clk_get(dev->dev, "i2c_ick");
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if (IS_ERR(dev->iclk)) {
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dev->iclk = NULL;
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@ -178,25 +226,33 @@ static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
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static void omap_i2c_unidle(struct omap_i2c_dev *dev)
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{
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WARN_ON(!dev->idle);
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if (dev->iclk != NULL)
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clk_enable(dev->iclk);
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clk_enable(dev->fclk);
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dev->idle = 0;
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if (dev->iestate)
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omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
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dev->idle = 0;
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}
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static void omap_i2c_idle(struct omap_i2c_dev *dev)
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{
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u16 iv;
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dev->idle = 1;
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WARN_ON(dev->idle);
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dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
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omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
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if (dev->rev1)
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if (dev->rev < OMAP_I2C_REV_2) {
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iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
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else
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} else {
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omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
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/* Flush posted write before the dev->idle store occurs */
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omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
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}
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dev->idle = 1;
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clk_disable(dev->fclk);
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if (dev->iclk != NULL)
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clk_disable(dev->iclk);
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@ -204,18 +260,20 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
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static int omap_i2c_init(struct omap_i2c_dev *dev)
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{
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u16 psc = 0;
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u16 psc = 0, scll = 0, sclh = 0;
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u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
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unsigned long fclk_rate = 12000000;
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unsigned long timeout;
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unsigned long internal_clk = 0;
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if (!dev->rev1) {
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omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
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if (dev->rev >= OMAP_I2C_REV_2) {
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omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
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/* For some reason we need to set the EN bit before the
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* reset done bit gets set. */
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timeout = jiffies + OMAP_I2C_TIMEOUT;
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
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while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
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OMAP_I2C_SYSS_RDONE)) {
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SYSS_RESETDONE_MASK)) {
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if (time_after(jiffies, timeout)) {
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dev_warn(dev->dev, "timeout waiting "
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"for controller reset\n");
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@ -223,6 +281,33 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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}
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msleep(1);
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}
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/* SYSC register is cleared by the reset; rewrite it */
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if (dev->rev == OMAP_I2C_REV_ON_2430) {
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omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
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SYSC_AUTOIDLE_MASK);
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} else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
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u32 v;
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v = SYSC_AUTOIDLE_MASK;
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v |= SYSC_ENAWAKEUP_MASK;
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v |= (SYSC_IDLEMODE_SMART <<
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__ffs(SYSC_SIDLEMODE_MASK));
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v |= (SYSC_CLOCKACTIVITY_FCLK <<
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__ffs(SYSC_CLOCKACTIVITY_MASK));
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omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
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/*
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* Enabling all wakup sources to stop I2C freezing on
|
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* WFI instruction.
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* REVISIT: Some wkup sources might not be needed.
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*/
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omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
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OMAP_I2C_WE_ALL);
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}
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}
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
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@ -249,18 +334,55 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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psc = fclk_rate / 12000000;
|
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}
|
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|
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/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
|
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omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
|
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if (cpu_is_omap2430() || cpu_is_omap34xx()) {
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|
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/* HSI2C controller internal clk rate should be 19.2 Mhz */
|
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internal_clk = 19200;
|
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fclk_rate = clk_get_rate(dev->fclk) / 1000;
|
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|
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/* Compute prescaler divisor */
|
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psc = fclk_rate / internal_clk;
|
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psc = psc - 1;
|
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|
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/* If configured for High Speed */
|
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if (dev->speed > 400) {
|
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/* For first phase of HS mode */
|
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fsscll = internal_clk / (400 * 2) - 6;
|
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fssclh = internal_clk / (400 * 2) - 6;
|
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|
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/* For second phase of HS mode */
|
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hsscll = fclk_rate / (dev->speed * 2) - 6;
|
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hssclh = fclk_rate / (dev->speed * 2) - 6;
|
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} else {
|
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/* To handle F/S modes */
|
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fsscll = internal_clk / (dev->speed * 2) - 6;
|
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fssclh = internal_clk / (dev->speed * 2) - 6;
|
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}
|
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scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
|
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sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
|
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} else {
|
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/* Program desired operating rate */
|
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fclk_rate /= (psc + 1) * 1000;
|
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if (psc > 2)
|
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psc = 2;
|
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scll = fclk_rate / (dev->speed * 2) - 7 + psc;
|
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sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
|
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}
|
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|
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omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
|
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fclk_rate / (clock * 2) - 7 + psc);
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
|
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fclk_rate / (clock * 2) - 7 + psc);
|
||||
/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
|
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omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
|
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|
||||
/* SCL low and high time values */
|
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omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
|
||||
|
||||
if (dev->fifo_size)
|
||||
/* Note: setup required fifo size - 1 */
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
|
||||
(dev->fifo_size - 1) << 8 | /* RTRSH */
|
||||
OMAP_I2C_BUF_RXFIF_CLR |
|
||||
(dev->fifo_size - 1) | /* XTRSH */
|
||||
OMAP_I2C_BUF_TXFIF_CLR);
|
||||
|
||||
/* Take the I2C module out of reset: */
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
|
||||
|
|
@ -269,7 +391,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
|
|||
omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
|
||||
(OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
|
||||
OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
|
||||
OMAP_I2C_IE_AL));
|
||||
OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
|
||||
(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -316,19 +439,58 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
|
|||
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
|
||||
|
||||
/* Clear the FIFO Buffers */
|
||||
w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
|
||||
w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
|
||||
|
||||
init_completion(&dev->cmd_complete);
|
||||
dev->cmd_err = 0;
|
||||
|
||||
w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
|
||||
|
||||
/* High speed configuration */
|
||||
if (dev->speed > 400)
|
||||
w |= OMAP_I2C_CON_OPMODE_HS;
|
||||
|
||||
if (msg->flags & I2C_M_TEN)
|
||||
w |= OMAP_I2C_CON_XA;
|
||||
if (!(msg->flags & I2C_M_RD))
|
||||
w |= OMAP_I2C_CON_TRX;
|
||||
if (stop)
|
||||
|
||||
if (!dev->b_hw && stop)
|
||||
w |= OMAP_I2C_CON_STP;
|
||||
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
|
||||
|
||||
r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
|
||||
/*
|
||||
* Don't write stt and stp together on some hardware.
|
||||
*/
|
||||
if (dev->b_hw && stop) {
|
||||
unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
|
||||
u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
|
||||
while (con & OMAP_I2C_CON_STT) {
|
||||
con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
|
||||
|
||||
/* Let the user know if i2c is in a bad state */
|
||||
if (time_after(jiffies, delay)) {
|
||||
dev_err(dev->dev, "controller timed out "
|
||||
"waiting for start condition to finish\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
w |= OMAP_I2C_CON_STP;
|
||||
w &= ~OMAP_I2C_CON_STT;
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
|
||||
}
|
||||
|
||||
/*
|
||||
* REVISIT: We should abort the transfer on signals, but the bus goes
|
||||
* into arbitration and we're currently unable to recover from it.
|
||||
*/
|
||||
r = wait_for_completion_timeout(&dev->cmd_complete,
|
||||
OMAP_I2C_TIMEOUT);
|
||||
dev->buf_len = 0;
|
||||
if (r < 0)
|
||||
|
|
@ -376,7 +538,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
|||
|
||||
omap_i2c_unidle(dev);
|
||||
|
||||
if ((r = omap_i2c_wait_for_bb(dev)) < 0)
|
||||
r = omap_i2c_wait_for_bb(dev);
|
||||
if (r < 0)
|
||||
goto out;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
|
|
@ -411,6 +574,9 @@ omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
|
|||
omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
|
||||
}
|
||||
|
||||
/* rev1 devices are apparently only on some 15xx */
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
|
||||
static irqreturn_t
|
||||
omap_i2c_rev1_isr(int this_irq, void *dev_id)
|
||||
{
|
||||
|
|
@ -465,6 +631,9 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
|
|||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
#else
|
||||
#define omap_i2c_rev1_isr NULL
|
||||
#endif
|
||||
|
||||
static irqreturn_t
|
||||
omap_i2c_isr(int this_irq, void *dev_id)
|
||||
|
|
@ -472,7 +641,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
|
|||
struct omap_i2c_dev *dev = dev_id;
|
||||
u16 bits;
|
||||
u16 stat, w;
|
||||
int count = 0;
|
||||
int err, count = 0;
|
||||
|
||||
if (dev->idle)
|
||||
return IRQ_NONE;
|
||||
|
|
@ -487,39 +656,96 @@ omap_i2c_isr(int this_irq, void *dev_id)
|
|||
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
|
||||
|
||||
if (stat & OMAP_I2C_STAT_ARDY) {
|
||||
omap_i2c_complete_cmd(dev, 0);
|
||||
continue;
|
||||
err = 0;
|
||||
if (stat & OMAP_I2C_STAT_NACK) {
|
||||
err |= OMAP_I2C_STAT_NACK;
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
|
||||
OMAP_I2C_CON_STP);
|
||||
}
|
||||
if (stat & OMAP_I2C_STAT_RRDY) {
|
||||
if (stat & OMAP_I2C_STAT_AL) {
|
||||
dev_err(dev->dev, "Arbitration lost\n");
|
||||
err |= OMAP_I2C_STAT_AL;
|
||||
}
|
||||
if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
|
||||
OMAP_I2C_STAT_AL))
|
||||
omap_i2c_complete_cmd(dev, err);
|
||||
if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
|
||||
u8 num_bytes = 1;
|
||||
if (dev->fifo_size) {
|
||||
if (stat & OMAP_I2C_STAT_RRDY)
|
||||
num_bytes = dev->fifo_size;
|
||||
else
|
||||
num_bytes = omap_i2c_read_reg(dev,
|
||||
OMAP_I2C_BUFSTAT_REG);
|
||||
}
|
||||
while (num_bytes) {
|
||||
num_bytes--;
|
||||
w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
|
||||
if (dev->buf_len) {
|
||||
*dev->buf++ = w;
|
||||
dev->buf_len--;
|
||||
/* Data reg from 2430 is 8 bit wide */
|
||||
if (!cpu_is_omap2430() &&
|
||||
!cpu_is_omap34xx()) {
|
||||
if (dev->buf_len) {
|
||||
*dev->buf++ = w >> 8;
|
||||
dev->buf_len--;
|
||||
}
|
||||
} else
|
||||
dev_err(dev->dev, "RRDY IRQ while no data "
|
||||
}
|
||||
} else {
|
||||
if (stat & OMAP_I2C_STAT_RRDY)
|
||||
dev_err(dev->dev,
|
||||
"RRDY IRQ while no data"
|
||||
" requested\n");
|
||||
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
|
||||
if (stat & OMAP_I2C_STAT_RDR)
|
||||
dev_err(dev->dev,
|
||||
"RDR IRQ while no data"
|
||||
" requested\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
omap_i2c_ack_stat(dev,
|
||||
stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
|
||||
continue;
|
||||
}
|
||||
if (stat & OMAP_I2C_STAT_XRDY) {
|
||||
if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
|
||||
u8 num_bytes = 1;
|
||||
if (dev->fifo_size) {
|
||||
if (stat & OMAP_I2C_STAT_XRDY)
|
||||
num_bytes = dev->fifo_size;
|
||||
else
|
||||
num_bytes = omap_i2c_read_reg(dev,
|
||||
OMAP_I2C_BUFSTAT_REG);
|
||||
}
|
||||
while (num_bytes) {
|
||||
num_bytes--;
|
||||
w = 0;
|
||||
if (dev->buf_len) {
|
||||
w = *dev->buf++;
|
||||
dev->buf_len--;
|
||||
/* Data reg from 2430 is 8 bit wide */
|
||||
if (!cpu_is_omap2430() &&
|
||||
!cpu_is_omap34xx()) {
|
||||
if (dev->buf_len) {
|
||||
w |= *dev->buf++ << 8;
|
||||
dev->buf_len--;
|
||||
}
|
||||
} else
|
||||
dev_err(dev->dev, "XRDY IRQ while no "
|
||||
}
|
||||
} else {
|
||||
if (stat & OMAP_I2C_STAT_XRDY)
|
||||
dev_err(dev->dev,
|
||||
"XRDY IRQ while no "
|
||||
"data to send\n");
|
||||
if (stat & OMAP_I2C_STAT_XDR)
|
||||
dev_err(dev->dev,
|
||||
"XDR IRQ while no "
|
||||
"data to send\n");
|
||||
break;
|
||||
}
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
|
||||
omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
|
||||
}
|
||||
omap_i2c_ack_stat(dev,
|
||||
stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
|
||||
continue;
|
||||
}
|
||||
if (stat & OMAP_I2C_STAT_ROVR) {
|
||||
|
|
@ -527,18 +753,9 @@ omap_i2c_isr(int this_irq, void *dev_id)
|
|||
dev->cmd_err |= OMAP_I2C_STAT_ROVR;
|
||||
}
|
||||
if (stat & OMAP_I2C_STAT_XUDF) {
|
||||
dev_err(dev->dev, "Transmit overflow\n");
|
||||
dev_err(dev->dev, "Transmit underflow\n");
|
||||
dev->cmd_err |= OMAP_I2C_STAT_XUDF;
|
||||
}
|
||||
if (stat & OMAP_I2C_STAT_NACK) {
|
||||
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
|
||||
OMAP_I2C_CON_STP);
|
||||
}
|
||||
if (stat & OMAP_I2C_STAT_AL) {
|
||||
dev_err(dev->dev, "Arbitration lost\n");
|
||||
omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
|
||||
}
|
||||
}
|
||||
|
||||
return count ? IRQ_HANDLED : IRQ_NONE;
|
||||
|
|
@ -549,13 +766,15 @@ static const struct i2c_algorithm omap_i2c_algo = {
|
|||
.functionality = omap_i2c_func,
|
||||
};
|
||||
|
||||
static int
|
||||
static int __init
|
||||
omap_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_i2c_dev *dev;
|
||||
struct i2c_adapter *adap;
|
||||
struct resource *mem, *irq, *ioarea;
|
||||
void *isr;
|
||||
int r;
|
||||
u32 speed = 0;
|
||||
|
||||
/* NOTE: driver uses the static register mapping */
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
|
@ -576,17 +795,19 @@ omap_i2c_probe(struct platform_device *pdev)
|
|||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (clock > 200)
|
||||
clock = 400; /* Fast mode */
|
||||
else
|
||||
clock = 100; /* Standard mode */
|
||||
|
||||
dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
|
||||
if (!dev) {
|
||||
r = -ENOMEM;
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
if (pdev->dev.platform_data != NULL)
|
||||
speed = *(u32 *)pdev->dev.platform_data;
|
||||
else
|
||||
speed = 100; /* Defualt speed */
|
||||
|
||||
dev->speed = speed;
|
||||
dev->idle = 1;
|
||||
dev->dev = &pdev->dev;
|
||||
dev->irq = irq->start;
|
||||
dev->base = ioremap(mem->start, mem->end - mem->start + 1);
|
||||
|
|
@ -602,22 +823,39 @@ omap_i2c_probe(struct platform_device *pdev)
|
|||
|
||||
omap_i2c_unidle(dev);
|
||||
|
||||
if (cpu_is_omap15xx())
|
||||
dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
|
||||
dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
|
||||
|
||||
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
|
||||
u16 s;
|
||||
|
||||
/* Set up the fifo size - Get total size */
|
||||
s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
|
||||
dev->fifo_size = 0x8 << s;
|
||||
|
||||
/*
|
||||
* Set up notification threshold as half the total available
|
||||
* size. This is to ensure that we can handle the status on int
|
||||
* call back latencies.
|
||||
*/
|
||||
dev->fifo_size = (dev->fifo_size / 2);
|
||||
dev->b_hw = 1; /* Enable hardware fixes */
|
||||
}
|
||||
|
||||
/* reset ASAP, clearing any IRQs */
|
||||
omap_i2c_init(dev);
|
||||
|
||||
r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
|
||||
0, pdev->name, dev);
|
||||
isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
|
||||
r = request_irq(dev->irq, isr, 0, pdev->name, dev);
|
||||
|
||||
if (r) {
|
||||
dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
|
||||
goto err_unuse_clocks;
|
||||
}
|
||||
r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
|
||||
|
||||
dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
|
||||
pdev->id, r >> 4, r & 0xf, clock);
|
||||
pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
|
||||
|
||||
omap_i2c_idle(dev);
|
||||
|
||||
adap = &dev->adapter;
|
||||
i2c_set_adapdata(adap, dev);
|
||||
|
|
@ -635,8 +873,6 @@ omap_i2c_probe(struct platform_device *pdev)
|
|||
goto err_free_irq;
|
||||
}
|
||||
|
||||
omap_i2c_idle(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_irq:
|
||||
|
|
|
|||
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