gpio: aspeed: Add debounce support
Each GPIO in the Aspeed GPIO controller can choose one of four input debounce states: to disable debouncing for an input, or select from one of three programmable debounce timer values. Each GPIO in a four-bank-set is assigned one bit in each of two debounce configuration registers dedicated to the set, and selects a debounce state by configuring the two bits to select one of the four options. The limitation on debounce timer values is managed by mapping offsets onto a configured timer value and keeping count of the number of users a timer has. Timer values are configured on a first-come-first-served basis. A small twist in the hardware design is that the debounce configuration register numbering is reversed with respect to the binary representation of the debounce timer of interest (i.e. debounce register 1 represents bit 1, and debounce register 2 represents bit 0 of the timer numbering). Tested on an AST2500EVB with additional inspection under QEMU's romulus-bmc machine. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andrew Jeffery
Linus Walleij
Родитель
9d7163f516
Коммит
5ae4cb94b3
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@ -9,14 +9,18 @@
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <asm/div64.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/hashtable.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/gpio/driver.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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struct aspeed_bank_props {
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unsigned int bank;
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@ -29,59 +33,85 @@ struct aspeed_gpio_config {
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const struct aspeed_bank_props *props;
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};
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/*
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* @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
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* @timer_users: Tracks the number of users for each timer
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*
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* The @timer_users has four elements but the first element is unused. This is
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* to simplify accounting and indexing, as a zero value in @offset_timer
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* represents disabled debouncing for the GPIO. Any other value for an element
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* of @offset_timer is used as an index into @timer_users. This behaviour of
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* the zero value aligns with the behaviour of zero built from the timer
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* configuration registers (i.e. debouncing is disabled).
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*/
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struct aspeed_gpio {
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struct gpio_chip chip;
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spinlock_t lock;
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void __iomem *base;
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int irq;
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const struct aspeed_gpio_config *config;
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u8 *offset_timer;
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unsigned int timer_users[4];
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struct clk *clk;
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};
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struct aspeed_gpio_bank {
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uint16_t val_regs;
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uint16_t irq_regs;
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uint16_t debounce_regs;
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const char names[4][3];
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};
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static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
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static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
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{
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.val_regs = 0x0000,
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.irq_regs = 0x0008,
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.debounce_regs = 0x0040,
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.names = { "A", "B", "C", "D" },
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},
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{
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.val_regs = 0x0020,
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.irq_regs = 0x0028,
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.debounce_regs = 0x0048,
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.names = { "E", "F", "G", "H" },
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},
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{
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.val_regs = 0x0070,
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.irq_regs = 0x0098,
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.debounce_regs = 0x00b0,
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.names = { "I", "J", "K", "L" },
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},
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{
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.val_regs = 0x0078,
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.irq_regs = 0x00e8,
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.debounce_regs = 0x0100,
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.names = { "M", "N", "O", "P" },
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},
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{
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.val_regs = 0x0080,
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.irq_regs = 0x0118,
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.debounce_regs = 0x0130,
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.names = { "Q", "R", "S", "T" },
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},
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{
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.val_regs = 0x0088,
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.irq_regs = 0x0148,
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.debounce_regs = 0x0160,
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.names = { "U", "V", "W", "X" },
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},
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{
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.val_regs = 0x01E0,
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.irq_regs = 0x0178,
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.debounce_regs = 0x0190,
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.names = { "Y", "Z", "AA", "AB" },
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},
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{
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.val_regs = 0x01E8,
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.irq_regs = 0x01A8,
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.debounce_regs = 0x01c0,
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.names = { "AC", "", "", "" },
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},
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};
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@ -99,6 +129,13 @@ static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
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#define GPIO_IRQ_TYPE2 0x0c
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#define GPIO_IRQ_STATUS 0x10
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#define GPIO_DEBOUNCE_SEL1 0x00
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#define GPIO_DEBOUNCE_SEL2 0x04
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#define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
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#define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
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#define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
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static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
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{
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unsigned int bank = GPIO_BANK(offset);
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@ -144,6 +181,7 @@ static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
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}
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#define have_irq(g, o) have_input((g), (o))
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#define have_debounce(g, o) have_input((g), (o))
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static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
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{
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@ -506,6 +544,227 @@ static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
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pinctrl_free_gpio(chip->base + offset);
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}
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static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio,
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const struct aspeed_gpio_bank *bank,
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unsigned int reg)
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{
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return gpio->base + bank->debounce_regs + reg;
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}
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static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
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u32 *cycles)
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{
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u64 rate;
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u64 n;
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u32 r;
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rate = clk_get_rate(gpio->clk);
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if (!rate)
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return -ENOTSUPP;
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n = rate * usecs;
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r = do_div(n, 1000000);
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if (n >= U32_MAX)
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return -ERANGE;
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/* At least as long as the requested time */
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*cycles = n + (!!r);
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return 0;
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}
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/* Call under gpio->lock */
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static int register_allocated_timer(struct aspeed_gpio *gpio,
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unsigned int offset, unsigned int timer)
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{
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if (WARN(gpio->offset_timer[offset] != 0,
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"Offset %d already allocated timer %d\n",
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offset, gpio->offset_timer[offset]))
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return -EINVAL;
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if (WARN(gpio->timer_users[timer] == UINT_MAX,
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"Timer user count would overflow\n"))
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return -EPERM;
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gpio->offset_timer[offset] = timer;
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gpio->timer_users[timer]++;
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return 0;
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}
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/* Call under gpio->lock */
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static int unregister_allocated_timer(struct aspeed_gpio *gpio,
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unsigned int offset)
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{
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if (WARN(gpio->offset_timer[offset] == 0,
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"No timer allocated to offset %d\n", offset))
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return -EINVAL;
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if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
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"No users recorded for timer %d\n",
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gpio->offset_timer[offset]))
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return -EINVAL;
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gpio->timer_users[gpio->offset_timer[offset]]--;
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gpio->offset_timer[offset] = 0;
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return 0;
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}
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/* Call under gpio->lock */
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static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
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unsigned int offset)
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{
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return gpio->offset_timer[offset] > 0;
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}
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/* Call under gpio->lock */
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static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
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unsigned int timer)
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{
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const struct aspeed_gpio_bank *bank = to_bank(offset);
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const u32 mask = GPIO_BIT(offset);
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void __iomem *addr;
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u32 val;
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addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL1);
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val = ioread32(addr);
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iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
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addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL2);
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val = ioread32(addr);
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iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
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}
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static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
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unsigned long usecs)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(chip);
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u32 requested_cycles;
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unsigned long flags;
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int rc;
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int i;
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rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
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if (rc < 0) {
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dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
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usecs, clk_get_rate(gpio->clk), rc);
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return rc;
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}
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spin_lock_irqsave(&gpio->lock, flags);
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if (timer_allocation_registered(gpio, offset)) {
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rc = unregister_allocated_timer(gpio, offset);
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if (rc < 0)
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goto out;
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}
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/* Try to find a timer already configured for the debounce period */
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for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
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u32 cycles;
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cycles = ioread32(gpio->base + debounce_timers[i]);
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if (requested_cycles == cycles)
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break;
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}
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if (i == ARRAY_SIZE(debounce_timers)) {
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int j;
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/*
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* As there are no timers configured for the requested debounce
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* period, find an unused timer instead
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*/
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for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
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if (gpio->timer_users[j] == 0)
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break;
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}
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if (j == ARRAY_SIZE(gpio->timer_users)) {
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dev_warn(chip->parent,
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"Debounce timers exhausted, cannot debounce for period %luus\n",
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usecs);
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rc = -EPERM;
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/*
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* We already adjusted the accounting to remove @offset
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* as a user of its previous timer, so also configure
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* the hardware so @offset has timers disabled for
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* consistency.
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*/
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configure_timer(gpio, offset, 0);
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goto out;
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}
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i = j;
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iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
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}
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if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
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rc = -EINVAL;
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goto out;
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}
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register_allocated_timer(gpio, offset, i);
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configure_timer(gpio, offset, i);
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out:
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spin_unlock_irqrestore(&gpio->lock, flags);
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return rc;
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}
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static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(chip);
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unsigned long flags;
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int rc;
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spin_lock_irqsave(&gpio->lock, flags);
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rc = unregister_allocated_timer(gpio, offset);
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if (!rc)
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configure_timer(gpio, offset, 0);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return rc;
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}
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static int set_debounce(struct gpio_chip *chip, unsigned int offset,
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unsigned long usecs)
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{
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struct aspeed_gpio *gpio = gpiochip_get_data(chip);
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if (!have_debounce(gpio, offset))
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return -ENOTSUPP;
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if (usecs)
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return enable_debounce(chip, offset, usecs);
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return disable_debounce(chip, offset);
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}
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static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
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unsigned long config)
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{
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unsigned long param = pinconf_to_config_param(config);
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u32 arg = pinconf_to_config_argument(config);
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if (param == PIN_CONFIG_INPUT_DEBOUNCE)
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return set_debounce(chip, offset, arg);
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else if (param == PIN_CONFIG_BIAS_DISABLE ||
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param == PIN_CONFIG_BIAS_PULL_DOWN ||
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param == PIN_CONFIG_DRIVE_STRENGTH)
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return pinctrl_gpio_set_config(offset, config);
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return -ENOTSUPP;
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}
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/*
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* Any banks not specified in a struct aspeed_bank_props array are assumed to
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* have the properties:
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@ -565,8 +824,16 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
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if (!gpio_id)
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return -EINVAL;
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gpio->clk = of_clk_get(pdev->dev.of_node, 0);
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if (IS_ERR(gpio->clk)) {
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dev_warn(&pdev->dev,
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"No HPLL clock phandle provided, debouncing disabled\n");
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gpio->clk = NULL;
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}
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gpio->config = gpio_id->data;
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gpio->chip.parent = &pdev->dev;
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gpio->chip.ngpio = gpio->config->nr_gpios;
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gpio->chip.parent = &pdev->dev;
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gpio->chip.direction_input = aspeed_gpio_dir_in;
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@ -576,6 +843,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
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gpio->chip.free = aspeed_gpio_free;
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gpio->chip.get = aspeed_gpio_get;
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gpio->chip.set = aspeed_gpio_set;
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gpio->chip.set_config = aspeed_gpio_set_config;
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gpio->chip.label = dev_name(&pdev->dev);
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gpio->chip.base = -1;
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gpio->chip.irq_need_valid_mask = true;
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@ -584,6 +852,9 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
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if (rc < 0)
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return rc;
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gpio->offset_timer =
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devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
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return aspeed_gpio_setup_irqs(gpio, pdev);
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}
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