arm64: mm: rewrite ASID allocator and MM context-switching code
Our current switch_mm implementation suffers from a number of problems:
(1) The ASID allocator relies on IPIs to synchronise the CPUs on a
rollover event
(2) Because of (1), we cannot allocate ASIDs with interrupts disabled
and therefore make use of a TIF_SWITCH_MM flag to postpone the
actual switch to finish_arch_post_lock_switch
(3) We run context switch with a reserved (invalid) TTBR0 value, even
though the ASID and pgd are updated atomically
(4) We take a global spinlock (cpu_asid_lock) during context-switch
(5) We use h/w broadcast TLB operations when they are not required
(e.g. in flush_context)
This patch addresses these problems by rewriting the ASID algorithm to
match the bitmap-based arch/arm/ implementation more closely. This in
turn allows us to remove much of the complications surrounding switch_mm,
including the ugly thread flag.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Will Deacon
Catalin Marinas
Родитель
8e63d38876
Коммит
5aec715d7d
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@ -17,15 +17,16 @@
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#define __ASM_MMU_H
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typedef struct {
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unsigned int id;
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raw_spinlock_t id_lock;
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void *vdso;
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atomic64_t id;
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void *vdso;
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} mm_context_t;
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#define INIT_MM_CONTEXT(name) \
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.context.id_lock = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
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#define ASID(mm) ((mm)->context.id & 0xffff)
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/*
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* This macro is only used by the TLBI code, which cannot race with an
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* ASID change and therefore doesn't need to reload the counter using
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* atomic64_read.
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*/
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#define ASID(mm) ((mm)->context.id.counter & 0xffff)
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extern void paging_init(void);
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extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
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@ -28,13 +28,6 @@
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#include <asm/cputype.h>
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#include <asm/pgtable.h>
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#define MAX_ASID_BITS 16
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extern unsigned int cpu_last_asid;
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void __new_context(struct mm_struct *mm);
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#ifdef CONFIG_PID_IN_CONTEXTIDR
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static inline void contextidr_thread_switch(struct task_struct *next)
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{
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@ -96,66 +89,19 @@ static inline void cpu_set_default_tcr_t0sz(void)
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: "r"(TCR_T0SZ(VA_BITS)), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH));
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}
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static inline void switch_new_context(struct mm_struct *mm)
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{
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unsigned long flags;
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__new_context(mm);
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local_irq_save(flags);
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cpu_switch_mm(mm->pgd, mm);
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local_irq_restore(flags);
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}
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static inline void check_and_switch_context(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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/*
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* Required during context switch to avoid speculative page table
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* walking with the wrong TTBR.
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*/
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cpu_set_reserved_ttbr0();
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if (!((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS))
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/*
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* The ASID is from the current generation, just switch to the
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* new pgd. This condition is only true for calls from
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* context_switch() and interrupts are already disabled.
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*/
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cpu_switch_mm(mm->pgd, mm);
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else if (irqs_disabled())
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/*
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* Defer the new ASID allocation until after the context
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* switch critical region since __new_context() cannot be
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* called with interrupts disabled.
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*/
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set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
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else
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/*
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* That is a direct call to switch_mm() or activate_mm() with
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* interrupts enabled and a new context.
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*/
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switch_new_context(mm);
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}
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#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
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/*
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* It would be nice to return ASIDs back to the allocator, but unfortunately
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* that introduces a race with a generation rollover where we could erroneously
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* free an ASID allocated in a future generation. We could workaround this by
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* freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
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* but we'd then need to make sure that we didn't dirty any TLBs afterwards.
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* Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
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* take CPU migration into account.
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*/
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#define destroy_context(mm) do { } while(0)
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void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
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#define finish_arch_post_lock_switch \
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finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
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struct mm_struct *mm = current->mm;
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unsigned long flags;
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__new_context(mm);
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local_irq_save(flags);
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cpu_switch_mm(mm->pgd, mm);
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local_irq_restore(flags);
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}
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}
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#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
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/*
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* This is called when "tsk" is about to enter lazy TLB mode.
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@ -111,7 +111,6 @@ static inline struct thread_info *current_thread_info(void)
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#define TIF_RESTORE_SIGMASK 20
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#define TIF_SINGLESTEP 21
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#define TIF_32BIT 22 /* 32bit process */
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#define TIF_SWITCH_MM 23 /* deferred switch_mm */
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#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
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@ -60,7 +60,7 @@ int main(void)
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DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
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DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
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BLANK();
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DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id));
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DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
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BLANK();
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DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
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DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
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@ -48,7 +48,6 @@ static struct mm_struct efi_mm = {
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.mmap_sem = __RWSEM_INITIALIZER(efi_mm.mmap_sem),
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.page_table_lock = __SPIN_LOCK_UNLOCKED(efi_mm.page_table_lock),
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.mmlist = LIST_HEAD_INIT(efi_mm.mmlist),
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INIT_MM_CONTEXT(efi_mm)
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};
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static int uefi_debug __initdata;
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@ -17,135 +17,187 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/percpu.h>
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#include <asm/cpufeature.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/cachetype.h>
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#define asid_bits(reg) \
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(((read_cpuid(ID_AA64MMFR0_EL1) & 0xf0) >> 2) + 8)
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#define ASID_FIRST_VERSION (1 << MAX_ASID_BITS)
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static u32 asid_bits;
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static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
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unsigned int cpu_last_asid = ASID_FIRST_VERSION;
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/*
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* We fork()ed a process, and we need a new context for the child to run in.
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*/
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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mm->context.id = 0;
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raw_spin_lock_init(&mm->context.id_lock);
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}
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static atomic64_t asid_generation;
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static unsigned long *asid_map;
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static void flush_context(void)
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static DEFINE_PER_CPU(atomic64_t, active_asids);
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static DEFINE_PER_CPU(u64, reserved_asids);
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static cpumask_t tlb_flush_pending;
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#define ASID_MASK (~GENMASK(asid_bits - 1, 0))
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#define ASID_FIRST_VERSION (1UL << asid_bits)
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#define NUM_USER_ASIDS ASID_FIRST_VERSION
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static void flush_context(unsigned int cpu)
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{
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/* set the reserved TTBR0 before flushing the TLB */
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cpu_set_reserved_ttbr0();
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local_flush_tlb_all();
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int i;
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u64 asid;
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/* Update the list of reserved ASIDs and the ASID bitmap. */
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bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
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/*
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* Ensure the generation bump is observed before we xchg the
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* active_asids.
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*/
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smp_wmb();
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for_each_possible_cpu(i) {
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asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
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/*
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* If this CPU has already been through a
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* rollover, but hasn't run another task in
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* the meantime, we must preserve its reserved
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* ASID, as this is the only trace we have of
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* the process it is still running.
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*/
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if (asid == 0)
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asid = per_cpu(reserved_asids, i);
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__set_bit(asid & ~ASID_MASK, asid_map);
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per_cpu(reserved_asids, i) = asid;
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}
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/* Queue a TLB invalidate and flush the I-cache if necessary. */
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cpumask_setall(&tlb_flush_pending);
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if (icache_is_aivivt())
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__local_flush_icache_all();
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__flush_icache_all();
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}
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static void set_mm_context(struct mm_struct *mm, unsigned int asid)
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static int is_reserved_asid(u64 asid)
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{
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int cpu;
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for_each_possible_cpu(cpu)
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if (per_cpu(reserved_asids, cpu) == asid)
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return 1;
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return 0;
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}
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static u64 new_context(struct mm_struct *mm, unsigned int cpu)
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{
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static u32 cur_idx = 1;
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u64 asid = atomic64_read(&mm->context.id);
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u64 generation = atomic64_read(&asid_generation);
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if (asid != 0) {
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/*
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* If our current ASID was active during a rollover, we
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* can continue to use it and this was just a false alarm.
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*/
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if (is_reserved_asid(asid))
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return generation | (asid & ~ASID_MASK);
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/*
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* We had a valid ASID in a previous life, so try to re-use
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* it if possible.
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*/
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asid &= ~ASID_MASK;
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if (!__test_and_set_bit(asid, asid_map))
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goto bump_gen;
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}
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/*
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* Allocate a free ASID. If we can't find one, take a note of the
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* currently active ASIDs and mark the TLBs as requiring flushes.
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* We always count from ASID #1, as we use ASID #0 when setting a
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* reserved TTBR0 for the init_mm.
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*/
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asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
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if (asid != NUM_USER_ASIDS)
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goto set_asid;
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/* We're out of ASIDs, so increment the global generation count */
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generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
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&asid_generation);
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flush_context(cpu);
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/* We have at least 1 ASID per CPU, so this will always succeed */
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asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
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set_asid:
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__set_bit(asid, asid_map);
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cur_idx = asid;
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bump_gen:
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asid |= generation;
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cpumask_clear(mm_cpumask(mm));
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return asid;
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}
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void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
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{
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unsigned long flags;
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u64 asid;
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asid = atomic64_read(&mm->context.id);
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/*
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* Locking needed for multi-threaded applications where the same
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* mm->context.id could be set from different CPUs during the
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* broadcast. This function is also called via IPI so the
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* mm->context.id_lock has to be IRQ-safe.
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* The memory ordering here is subtle. We rely on the control
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* dependency between the generation read and the update of
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* active_asids to ensure that we are synchronised with a
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* parallel rollover (i.e. this pairs with the smp_wmb() in
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* flush_context).
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*/
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raw_spin_lock_irqsave(&mm->context.id_lock, flags);
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if (likely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
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/*
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* Old version of ASID found. Set the new one and reset
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* mm_cpumask(mm).
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*/
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mm->context.id = asid;
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cpumask_clear(mm_cpumask(mm));
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if (!((asid ^ atomic64_read(&asid_generation)) >> asid_bits)
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&& atomic64_xchg_relaxed(&per_cpu(active_asids, cpu), asid))
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goto switch_mm_fastpath;
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raw_spin_lock_irqsave(&cpu_asid_lock, flags);
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/* Check that our ASID belongs to the current generation. */
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asid = atomic64_read(&mm->context.id);
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if ((asid ^ atomic64_read(&asid_generation)) >> asid_bits) {
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asid = new_context(mm, cpu);
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atomic64_set(&mm->context.id, asid);
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}
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raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
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/*
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* Set the mm_cpumask(mm) bit for the current CPU.
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*/
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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}
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if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
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local_flush_tlb_all();
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/*
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* Reset the ASID on the current CPU. This function call is broadcast from the
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* CPU handling the ASID rollover and holding cpu_asid_lock.
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*/
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static void reset_context(void *info)
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{
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unsigned int asid;
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unsigned int cpu = smp_processor_id();
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struct mm_struct *mm = current->active_mm;
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atomic64_set(&per_cpu(active_asids, cpu), asid);
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cpumask_set_cpu(cpu, mm_cpumask(mm));
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raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
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/*
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* current->active_mm could be init_mm for the idle thread immediately
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* after secondary CPU boot or hotplug. TTBR0_EL1 is already set to
|
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* the reserved value, so no need to reset any context.
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*/
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if (mm == &init_mm)
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return;
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smp_rmb();
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asid = cpu_last_asid + cpu;
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flush_context();
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set_mm_context(mm, asid);
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/* set the new ASID */
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switch_mm_fastpath:
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cpu_switch_mm(mm->pgd, mm);
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}
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|
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void __new_context(struct mm_struct *mm)
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static int asids_init(void)
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{
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unsigned int asid;
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unsigned int bits = asid_bits();
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int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), 4);
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raw_spin_lock(&cpu_asid_lock);
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/*
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* Check the ASID again, in case the change was broadcast from another
|
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* CPU before we acquired the lock.
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*/
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if (!unlikely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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raw_spin_unlock(&cpu_asid_lock);
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return;
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}
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/*
|
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* At this point, it is guaranteed that the current mm (with an old
|
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* ASID) isn't active on any other CPU since the ASIDs are changed
|
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* simultaneously via IPI.
|
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*/
|
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asid = ++cpu_last_asid;
|
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|
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/*
|
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* If we've used up all our ASIDs, we need to start a new version and
|
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* flush the TLB.
|
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*/
|
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if (unlikely((asid & ((1 << bits) - 1)) == 0)) {
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/* increment the ASID version */
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cpu_last_asid += (1 << MAX_ASID_BITS) - (1 << bits);
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if (cpu_last_asid == 0)
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cpu_last_asid = ASID_FIRST_VERSION;
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asid = cpu_last_asid + smp_processor_id();
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flush_context();
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smp_wmb();
|
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smp_call_function(reset_context, NULL, 1);
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cpu_last_asid += NR_CPUS - 1;
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switch (fld) {
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default:
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pr_warn("Unknown ASID size (%d); assuming 8-bit\n", fld);
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/* Fallthrough */
|
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case 0:
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asid_bits = 8;
|
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break;
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case 2:
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asid_bits = 16;
|
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}
|
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|
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set_mm_context(mm, asid);
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raw_spin_unlock(&cpu_asid_lock);
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/* If we end up with more CPUs than ASIDs, expect things to crash */
|
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WARN_ON(NUM_USER_ASIDS < num_possible_cpus());
|
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atomic64_set(&asid_generation, ASID_FIRST_VERSION);
|
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asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map),
|
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GFP_KERNEL);
|
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if (!asid_map)
|
||||
panic("Failed to allocate bitmap for %lu ASIDs\n",
|
||||
NUM_USER_ASIDS);
|
||||
|
||||
pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS);
|
||||
return 0;
|
||||
}
|
||||
early_initcall(asids_init);
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ ENDPROC(cpu_do_resume)
|
|||
* - pgd_phys - physical address of new TTB
|
||||
*/
|
||||
ENTRY(cpu_do_switch_mm)
|
||||
mmid w1, x1 // get mm->context.id
|
||||
mmid x1, x1 // get mm->context.id
|
||||
bfi x0, x1, #48, #16 // set the ASID
|
||||
msr ttbr0_el1, x0 // set TTBR0
|
||||
isb
|
||||
|
|
|
|||
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