ssb: Fix order of definitions and some text space indents
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Rafał Miłecki
John W. Linville
Родитель
0a182fd88f
Коммит
5af5542885
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@ -245,7 +245,6 @@
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#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
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/* SPROM Revision 3 (inherits most data from rev 2) */
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#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
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#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
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#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
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#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
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@ -254,6 +253,7 @@
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#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
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#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
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#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
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#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
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#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
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#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
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#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
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@ -265,20 +265,29 @@
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#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
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/* SPROM Revision 4 */
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#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
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#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
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#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
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#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
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#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
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#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
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#define SSB_SPROM4_GPIOA_P1_SHIFT 8
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#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
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#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM4_GPIOB_P3_SHIFT 8
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#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
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#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
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#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
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#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
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#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
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#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
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#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
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#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
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#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
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#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
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#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
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#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
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#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
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#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
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#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
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#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
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#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
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#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
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#define SSB_SPROM4_AGAIN0_SHIFT 0
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@ -289,7 +298,6 @@
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#define SSB_SPROM4_AGAIN2_SHIFT 0
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#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
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#define SSB_SPROM4_AGAIN3_SHIFT 8
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#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
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#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
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#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
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#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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@ -298,14 +306,6 @@
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#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
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#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
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#define SSB_SPROM4_ITSSI_A_SHIFT 8
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#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
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#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
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#define SSB_SPROM4_GPIOA_P1_SHIFT 8
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#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
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#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM4_GPIOB_P3_SHIFT 8
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#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
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#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
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#define SSB_SPROM4_PA0B2 0x0086
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@ -314,10 +314,10 @@
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#define SSB_SPROM4_PA1B2 0x0092
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/* SPROM Revision 5 (inherits most data from rev 4) */
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#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
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#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
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#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
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#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
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#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
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#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
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#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
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@ -335,11 +335,19 @@
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#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
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#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
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#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
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#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
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#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
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#define SSB_SPROM8_GPIOA_P1_SHIFT 8
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#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
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#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM8_GPIOB_P3_SHIFT 8
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#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
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#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
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#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
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#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
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#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
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#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
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#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
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#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
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#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
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#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
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#define SSB_SPROM8_AGAIN0_SHIFT 0
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@ -350,14 +358,6 @@
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#define SSB_SPROM8_AGAIN2_SHIFT 0
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#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
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#define SSB_SPROM8_AGAIN3_SHIFT 8
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#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
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#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
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#define SSB_SPROM8_GPIOA_P1_SHIFT 8
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#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
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#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
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#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
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#define SSB_SPROM8_GPIOB_P3_SHIFT 8
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#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
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#define SSB_SPROM8_RSSISMF2G 0x000F
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#define SSB_SPROM8_RSSISMC2G 0x00F0
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