cxgb4: Add functions to read memory via PCIE memory window
This patch implements two new functions t4_mem_win_read and t4_memory_read. These new functions can be used to read memory via the PCIE memory window. Please note, for proper execution of these functions PCIE_MEM_ACCESS_BASE_WIN registers must be setup correctly like how setup_memwin in the cxgb4 driver does it. Signed-off-by: Jay Hernandez <jay@chelsio.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vipul Pandya
David S. Miller
Родитель
3eb4afbfce
Коммит
5afc8b84eb
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@ -664,6 +664,8 @@ int t4_wait_dev_ready(struct adapter *adap);
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int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
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struct link_config *lc);
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int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
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int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
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__be32 *buf);
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int t4_seeprom_wp(struct adapter *adapter, bool enable);
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int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
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int t4_check_fw_version(struct adapter *adapter);
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@ -330,6 +330,143 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
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return 0;
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}
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/*
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* t4_mem_win_rw - read/write memory through PCIE memory window
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* @adap: the adapter
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* @addr: address of first byte requested
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* @data: MEMWIN0_APERTURE bytes of data containing the requested address
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* @dir: direction of transfer 1 => read, 0 => write
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*
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* Read/write MEMWIN0_APERTURE bytes of data from MC starting at a
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* MEMWIN0_APERTURE-byte-aligned address that covers the requested
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* address @addr.
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*/
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static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
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{
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int i;
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/*
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* Setup offset into PCIE memory window. Address must be a
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* MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to
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* ensure that changes propagate before we attempt to use the new
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* values.)
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*/
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t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
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addr & ~(MEMWIN0_APERTURE - 1));
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t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
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/* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
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for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
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if (dir)
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*data++ = t4_read_reg(adap, (MEMWIN0_BASE + i));
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else
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t4_write_reg(adap, (MEMWIN0_BASE + i), *data++);
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}
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return 0;
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}
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/**
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* t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
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* @adap: the adapter
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* @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
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* @addr: address within indicated memory type
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* @len: amount of memory to transfer
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* @buf: host memory buffer
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* @dir: direction of transfer 1 => read, 0 => write
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*
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* Reads/writes an [almost] arbitrary memory region in the firmware: the
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* firmware memory address, length and host buffer must be aligned on
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* 32-bit boudaries. The memory is transferred as a raw byte sequence
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* from/to the firmware's memory. If this memory contains data
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* structures which contain multi-byte integers, it's the callers
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* responsibility to perform appropriate byte order conversions.
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*/
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static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
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__be32 *buf, int dir)
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{
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u32 pos, start, end, offset, memoffset;
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int ret;
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/*
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* Argument sanity checks ...
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*/
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if ((addr & 0x3) || (len & 0x3))
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return -EINVAL;
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/*
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* Offset into the region of memory which is being accessed
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* MEM_EDC0 = 0
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* MEM_EDC1 = 1
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* MEM_MC = 2
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*/
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memoffset = (mtype * (5 * 1024 * 1024));
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/* Determine the PCIE_MEM_ACCESS_OFFSET */
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addr = addr + memoffset;
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/*
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* The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes
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* at a time so we need to round down the start and round up the end.
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* We'll start copying out of the first line at (addr - start) a word
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* at a time.
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*/
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start = addr & ~(MEMWIN0_APERTURE-1);
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end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1);
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offset = (addr - start)/sizeof(__be32);
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for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) {
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__be32 data[MEMWIN0_APERTURE/sizeof(__be32)];
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/*
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* If we're writing, copy the data from the caller's memory
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* buffer
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*/
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if (!dir) {
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/*
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* If we're doing a partial write, then we need to do
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* a read-modify-write ...
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*/
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if (offset || len < MEMWIN0_APERTURE) {
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ret = t4_mem_win_rw(adap, pos, data, 1);
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if (ret)
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return ret;
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}
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while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
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len > 0) {
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data[offset++] = *buf++;
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len -= sizeof(__be32);
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}
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}
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/*
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* Transfer a block of memory and bail if there's an error.
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*/
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ret = t4_mem_win_rw(adap, pos, data, dir);
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if (ret)
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return ret;
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/*
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* If we're reading, copy the data into the caller's memory
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* buffer.
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*/
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if (dir)
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while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
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len > 0) {
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*buf++ = data[offset++];
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len -= sizeof(__be32);
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}
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}
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return 0;
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}
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int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
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__be32 *buf)
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{
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return t4_memory_rw(adap, mtype, addr, len, buf, 0);
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}
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#define EEPROM_STAT_ADDR 0x7bfc
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#define VPD_BASE 0
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#define VPD_LEN 512
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@ -58,6 +58,7 @@ enum {
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enum {
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SF_PAGE_SIZE = 256, /* serial flash page size */
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SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
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};
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enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
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@ -137,4 +138,83 @@ struct rsp_ctrl {
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#define QINTR_CNT_EN 0x1
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#define QINTR_TIMER_IDX(x) ((x) << 1)
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#define QINTR_TIMER_IDX_GET(x) (((x) >> 1) & 0x7)
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/*
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* Flash layout.
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*/
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#define FLASH_START(start) ((start) * SF_SEC_SIZE)
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#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
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enum {
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/*
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* Various Expansion-ROM boot images, etc.
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*/
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FLASH_EXP_ROM_START_SEC = 0,
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FLASH_EXP_ROM_NSECS = 6,
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FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
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FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
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/*
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* iSCSI Boot Firmware Table (iBFT) and other driver-related
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* parameters ...
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*/
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FLASH_IBFT_START_SEC = 6,
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FLASH_IBFT_NSECS = 1,
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FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
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FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
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/*
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* Boot configuration data.
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*/
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FLASH_BOOTCFG_START_SEC = 7,
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FLASH_BOOTCFG_NSECS = 1,
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FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
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FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
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/*
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* Location of firmware image in FLASH.
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*/
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FLASH_FW_START_SEC = 8,
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FLASH_FW_NSECS = 8,
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FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
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FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
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/*
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* iSCSI persistent/crash information.
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*/
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FLASH_ISCSI_CRASH_START_SEC = 29,
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FLASH_ISCSI_CRASH_NSECS = 1,
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FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
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FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
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/*
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* FCoE persistent/crash information.
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*/
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FLASH_FCOE_CRASH_START_SEC = 30,
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FLASH_FCOE_CRASH_NSECS = 1,
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FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
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FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
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/*
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* Location of Firmware Configuration File in FLASH. Since the FPGA
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* "FLASH" is smaller we need to store the Configuration File in a
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* different location -- which will overlap the end of the firmware
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* image if firmware ever gets that large ...
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*/
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FLASH_CFG_START_SEC = 31,
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FLASH_CFG_NSECS = 1,
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FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
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FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
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FLASH_FPGA_CFG_START_SEC = 15,
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FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
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/*
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* Sectors 32-63 are reserved for FLASH failover.
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*/
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};
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#undef FLASH_START
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#undef FLASH_MAX_SIZE
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#endif /* __T4_HW_H */
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