mtd: nand: reintroduce NAND_NO_READRDY as NAND_NEED_READRDY
This partially reverts commit 1696e6bc2a
("mtd: nand: kill NAND_NO_READRDY").
In that patch I overlooked a few things.
The original documentation for NAND_NO_READRDY included "True for all
large page devices, as they do not support autoincrement." I was
conflating "not support autoincrement" with the NAND_NO_AUTOINCR option,
which was in fact doing nothing. So, when I dropped NAND_NO_AUTOINCR, I
concluded that I then could harmlessly drop NAND_NO_READRDY. But of
course the fact the NAND_NO_AUTOINCR was doing nothing didn't mean
NAND_NO_READRDY was doing nothing...
So, NAND_NO_READRDY is re-introduced as NAND_NEED_READRDY and applied
only to those few remaining small-page NAND which needed it in the first
place.
Cc: stable@kernel.org [3.5+]
Reported-by: Alexander Shiyan <shc_work@mail.ru>
Tested-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Brian Norris
David Woodhouse
Родитель
91d542f4dc
Коммит
5bc7c33ca9
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@ -1523,6 +1523,14 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
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oobreadlen -= toread;
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}
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}
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if (chip->options & NAND_NEED_READRDY) {
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/* Apply delay or wait for ready/busy pin */
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if (!chip->dev_ready)
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udelay(chip->chip_delay);
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else
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nand_wait_ready(mtd);
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}
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} else {
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memcpy(buf, chip->buffers->databuf + col, bytes);
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buf += bytes;
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@ -1787,6 +1795,14 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
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len = min(len, readlen);
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buf = nand_transfer_oob(chip, buf, ops, len);
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if (chip->options & NAND_NEED_READRDY) {
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/* Apply delay or wait for ready/busy pin */
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if (!chip->dev_ready)
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udelay(chip->chip_delay);
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else
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nand_wait_ready(mtd);
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}
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readlen -= len;
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if (!readlen)
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break;
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@ -22,49 +22,51 @@
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* 512 512 Byte page size
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*/
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struct nand_flash_dev nand_flash_ids[] = {
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#define SP_OPTIONS NAND_NEED_READRDY
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#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
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#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
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{"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
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{"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
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{"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
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{"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
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{"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
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{"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
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{"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
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{"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
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{"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
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{"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
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{"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, SP_OPTIONS},
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{"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, SP_OPTIONS},
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{"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, SP_OPTIONS},
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{"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, SP_OPTIONS},
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{"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, SP_OPTIONS},
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{"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, SP_OPTIONS},
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{"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, SP_OPTIONS},
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{"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, SP_OPTIONS},
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{"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, SP_OPTIONS},
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{"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, SP_OPTIONS},
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{"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
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{"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
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{"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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{"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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{"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, SP_OPTIONS},
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{"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, SP_OPTIONS},
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{"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, SP_OPTIONS16},
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{"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, SP_OPTIONS16},
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#endif
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{"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
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{"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
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{"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, SP_OPTIONS},
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{"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, SP_OPTIONS},
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{"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, SP_OPTIONS16},
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{"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, SP_OPTIONS16},
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{"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
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{"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
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{"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, SP_OPTIONS},
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{"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, SP_OPTIONS},
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{"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, SP_OPTIONS16},
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{"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, SP_OPTIONS16},
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{"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
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{"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
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{"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, SP_OPTIONS},
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{"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, SP_OPTIONS},
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{"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, SP_OPTIONS16},
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{"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, SP_OPTIONS16},
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{"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
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{"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
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{"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
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{"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, SP_OPTIONS},
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{"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, SP_OPTIONS},
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{"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, SP_OPTIONS},
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{"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, SP_OPTIONS16},
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{"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, SP_OPTIONS16},
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{"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, SP_OPTIONS16},
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{"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, SP_OPTIONS16},
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{"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
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{"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, SP_OPTIONS},
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/*
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* These are the new chips with large page size. The pagesize and the
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@ -187,6 +187,13 @@ typedef enum {
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* This happens with the Renesas AG-AND chips, possibly others.
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*/
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#define BBT_AUTO_REFRESH 0x00000080
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/*
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* Chip requires ready check on read (for auto-incremented sequential read).
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* True only for small page devices; large page devices do not support
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* autoincrement.
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*/
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#define NAND_NEED_READRDY 0x00000100
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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