arm64: dts: add support for Marvell cn9130-crb platform
The Marvell reference platform CN9130-CRB is a small form factor board in a metal case. The platform is based on CN9130 SoC with addition of 8 Gigabit ports SOHO Ethernet switch. The reference platform features the following: * Up to 4 CPU cores ARMv8 Cortex-A72 CPU * CPU core operating speed of up to 2.2GHz * DDR4 DIMM – 8GB 64bit+ECC @ 2400Mhz. * 1x eMMC 8GB device * 1x uSD card 4 bits port on CP * 1x 128MB SPI NOR flash memory * 1x USB 3.0 Host port (Type A) * 1x SATA Gen3 via M.2 * 1x USB 3.0 via M.2 * 1x SIM card slot * 1x 1G Ethernet port via RGMII * 1x 10G switch port over SFP+ connector * 8x 1G ports through 88E6393X switch via XFI * 1x 2.5G/1G/100M/10M port via HS_SGMII * 1x PCI Express (PCIe)x1 Gen 3.0 * 1x PCI Express (PCIe)x4 Gen 3.0 via NVMe M.2 * JTAG port The CRB board uses MCP23017 i2c pin controller that drives the onboard eMMC abd USB 3,0 port power lines. The following configuration should be enabled for this controller support: CONFIG_PINCTRL_MCP23S08=y The plaform supports two HW configurations - "A" and "B" CN9130-CRB-A * AP-MPP configuration: SDIO, UART * CP0 Serdes configuration: * Lane0-3: NVMe (PCIe x4) * Lane4: XFI * Lane5: HS_SGMII 2. CN9130-CRB-B * AP-MPP configuration: SDIO, UART * CP0-MPP configuration: RGMII, SDIO, I2C0, I2C1, SMI, XSMI * CP0 Serdes configuration: * Lane0: PCIe x1 * Lane1: USB3_0 x1 * Lane2: SATA x1 * Lane3: USB3_1 x1 * Lane4: XFI * Lane5: HS_SGMII Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Konstantin Porotchkin
Gregory CLEMENT
Родитель
f3200db5c6
Коммит
5c0ee54723
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@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
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@ -0,0 +1,38 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include "cn9130-crb.dtsi"
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/ {
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model = "Marvell Armada CN9130-CRB-A";
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};
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&cp0_pcie0 {
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status = "okay";
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num-lanes = <4>;
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num-viewport = <8>;
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy0 0
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&cp0_comphy1 0
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&cp0_comphy2 0
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&cp0_comphy3 0>;
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iommu-map =
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<0x0 &smmu 0x480 0x20>,
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<0x100 &smmu 0x4a0 0x20>,
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<0x200 &smmu 0x4c0 0x20>;
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iommu-map-mask = <0x031f>;
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};
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&cp0_usb3_0 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy0>;
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phy-names = "usb";
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};
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&cp0_usb3_1 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy1>;
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phy-names = "usb";
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};
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@ -0,0 +1,46 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include "cn9130-crb.dtsi"
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/ {
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model = "Marvell Armada CN9130-CRB-B";
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};
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&cp0_pcie0 {
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status = "okay";
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num-lanes = <1>;
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num-viewport = <8>;
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy0 0>;
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iommu-map =
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<0x0 &smmu 0x480 0x20>,
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<0x100 &smmu 0x4a0 0x20>,
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<0x200 &smmu 0x4c0 0x20>;
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iommu-map-mask = <0x031f>;
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};
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&cp0_sata0 {
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status = "okay";
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sata-port@0 {
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status = "okay";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy2 0>;
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};
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};
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&cp0_usb3_0 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy0>;
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phy-names = "usb";
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phys = <&cp0_comphy1 0>;
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};
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&cp0_usb3_1 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy1>;
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phy-names = "usb";
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phys = <&cp0_comphy3 1>;
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};
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@ -0,0 +1,222 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include "cn9130.dtsi" /* include SoC device tree */
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#include <dt-bindings/gpio/gpio.h>
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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i2c0 = &cp0_i2c0;
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp0_eth1;
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ethernet2 = &cp0_eth2;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "ap0_mmc_vccq";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1
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3300000 0x0>;
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};
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cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
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compatible = "regulator-fixed";
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regulator-name = "cp0-xhci1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
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};
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cp0_usb3_0_phy0: cp0_usb3_phy0 {
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compatible = "usb-nop-xceiv";
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};
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cp0_usb3_0_phy1: cp0_usb3_phy1 {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&cp0_reg_usb3_vbus1>;
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};
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cp0_reg_sd_vccq: cp0_sd_vccq@0 {
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compatible = "regulator-gpio";
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regulator-name = "cp0_sd_vccq";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x1
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3300000 0x0>;
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};
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cp0_reg_sd_vcc: cp0_sd_vcc@0 {
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compatible = "regulator-fixed";
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regulator-name = "cp0_sd_vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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};
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&uart0 {
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status = "okay";
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};
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/* on-board eMMC U6 */
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&ap_sdhci0 {
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pinctrl-names = "default";
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bus-width = <8>;
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status = "okay";
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mmc-ddr-1_8v;
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vqmmc-supply = <&ap0_reg_mmc_vccq>;
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};
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&cp0_syscon0 {
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cp0_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = "mpp37", "mpp38";
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marvell,function = "i2c0";
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = "mpp35", "mpp36";
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marvell,function = "i2c1";
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};
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cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
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marvell,pins = "mpp55";
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marvell,function = "gpio";
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};
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cp0_sdhci_pins: cp0-sdhi-pins-0 {
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marvell,pins = "mpp56", "mpp57", "mpp58",
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"mpp59", "mpp60", "mpp61";
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marvell,function = "sdio";
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};
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cp0_spi0_pins: cp0-spi-pins-0 {
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marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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};
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};
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};
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&cp0_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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expander0: mcp23x17@20 {
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compatible = "microchip,mcp23017";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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status = "okay";
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};
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};
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&cp0_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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clock-frequency = <100000>;
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status = "okay";
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};
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&cp0_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins
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&cp0_sdhci_cd_pins_crb>;
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bus-width = <4>;
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cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
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vqmmc-supply = <&cp0_reg_sd_vccq>;
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vmmc-supply = <&cp0_reg_sd_vcc>;
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status = "okay";
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};
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&cp0_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi0_pins>;
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reg = <0x700680 0x50>, /* control */
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<0x2000000 0x1000000>; /* CS0 */
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status = "okay";
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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/* On-board MUX does not allow higher frequencies */
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xe00000>;
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};
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};
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};
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};
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&cp0_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&cp0_xmdio {
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status = "okay";
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nbaset_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth0 {
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/* This port is connected to 88E6393X switch */
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status = "okay";
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phy-mode = "10gbase-kr";
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managed = "in-band-status";
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phys = <&cp0_comphy4 0>;
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};
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&cp0_eth1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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&cp0_eth2 {
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/* This port uses "2500base-t" phy-mode */
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status = "disabled";
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phy = <&nbaset_phy0>;
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phys = <&cp0_comphy5 2>;
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};
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