irqchip core changes for v4.5
- renesas-intc-irqpin: Remove platform code, improve clock handling - sunxi-nmi: Extend NMI support to include A80 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJWesk9AAoJEP45WPkGe8ZnHz4QAL0yHVogWn/ggUcMl+B+UF6J 0RhiaVupNM7fvHP8xShqYUTn/f5j4OqkfAjKxN46uaa6a5LcL3Oq9fvZJ2IhYT8u MKoeBfDFLxjQ/ua58xs7tiloXxrk2DMBhm1+w0w7n0HRGQL5OEVX6hC08k/5K3X0 bOUEwU6ICJRzzxYOm9J2tXulfH6iCGurPbojk6x1sefOOeRbo48xIHWZ2wrDKpGD GHpmYA215+kfwibFH5eXojonRVt7R5YvGo9SZD48+NZv0l5CfC3v7QG8IsX0sFID rhwUVYo1LJ5lQlg0GOwRHVORSnTodMmiD7N6+aPJ90H0PrukA4J4CPZJydZfiJMa RXL5c7SDN/tJ0EzITSC63VQ06/kada2/I+w7jJesSAn44M+tyMx3zt5ZPLSU+MXn gpXTyVRQ8p068Eed/c946tz/rFoZJBE0CkpA++cYS3dc1ljPA3vt3CdaeH7AN29T nNW7qkVEQogZwC1Cjs3KXDmfsARlVmKfQ1zfoPftIr6Qh7xkXZL9m9lLJreZbtNj 3FgAoLQG/5WomzuBy46b8iMVfhst8tzL4K29xnMubYn79ir7rfd8JGqP8DZCFyNM IBzTJdDKBp1Digguybev3xfwNqdIOd3dXQwhqRF/TeQhsVuN0EcCeGD+DTdH17h2 4Pt/izUaD64pYeyV9USU =PJ3c -----END PGP SIGNATURE----- Merge tag 'irqchip-core-v4.5' of git://git.infradead.org/users/jcooper/linux into irq/core Pull irqchip core changes for v4.5 from Jason Cooper: - renesas-intc-irqpin: Remove platform code, improve clock handling - sunxi-nmi: Extend NMI support to include A80
This commit is contained in:
Thomas Gleixner
Коммит
5c4acd97e8
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@ -4,7 +4,7 @@ Allwinner Sunxi NMI Controller
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Required properties:
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- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
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"allwinner,sun6i-a31-sc-nmi"
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"allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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@ -31,7 +31,6 @@
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/pm_runtime.h>
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#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
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@ -75,18 +74,20 @@ struct intc_irqpin_irq {
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struct intc_irqpin_priv {
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struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
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struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
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struct renesas_intc_irqpin_config config;
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unsigned int number_of_irqs;
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unsigned int sense_bitfield_width;
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struct platform_device *pdev;
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struct irq_chip irq_chip;
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struct irq_domain *irq_domain;
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struct clk *clk;
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bool shared_irqs;
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unsigned shared_irqs:1;
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unsigned needs_clk:1;
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u8 shared_irq_mask;
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};
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struct intc_irqpin_irlm_config {
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struct intc_irqpin_config {
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unsigned int irlm_bit;
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unsigned needs_irlm:1;
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unsigned needs_clk:1;
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};
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static unsigned long intc_irqpin_read32(void __iomem *iomem)
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@ -171,7 +172,7 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
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static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
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{
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/* The SENSE register is assumed to be 32-bit. */
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int bitfield_width = p->config.sense_bitfield_width;
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int bitfield_width = p->sense_bitfield_width;
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int shift = 32 - (irq + 1) * bitfield_width;
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dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
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@ -361,8 +362,15 @@ static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
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.xlate = irq_domain_xlate_twocell,
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};
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static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a777x = {
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static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
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.irlm_bit = 23, /* ICR0.IRLM0 */
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.needs_irlm = 1,
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.needs_clk = 0,
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};
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static const struct intc_irqpin_config intc_irqpin_rmobile = {
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.needs_irlm = 0,
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.needs_clk = 1,
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};
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static const struct of_device_id intc_irqpin_dt_ids[] = {
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@ -371,14 +379,18 @@ static const struct of_device_id intc_irqpin_dt_ids[] = {
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.data = &intc_irqpin_irlm_r8a777x },
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{ .compatible = "renesas,intc-irqpin-r8a7779",
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.data = &intc_irqpin_irlm_r8a777x },
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{ .compatible = "renesas,intc-irqpin-r8a7740",
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.data = &intc_irqpin_rmobile },
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{ .compatible = "renesas,intc-irqpin-sh73a0",
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.data = &intc_irqpin_rmobile },
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{},
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};
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MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
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static int intc_irqpin_probe(struct platform_device *pdev)
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{
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const struct intc_irqpin_config *config = NULL;
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struct device *dev = &pdev->dev;
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struct renesas_intc_irqpin_config *pdata = dev->platform_data;
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const struct of_device_id *of_id;
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struct intc_irqpin_priv *p;
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struct intc_irqpin_iomem *i;
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@ -388,6 +400,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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void (*enable_fn)(struct irq_data *d);
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void (*disable_fn)(struct irq_data *d);
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const char *name = dev_name(dev);
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bool control_parent;
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unsigned int nirqs;
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int ref_irq;
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int ret;
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int k;
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@ -399,23 +413,28 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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}
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/* deal with driver instance configuration */
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if (pdata) {
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memcpy(&p->config, pdata, sizeof(*pdata));
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} else {
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of_property_read_u32(dev->of_node, "sense-bitfield-width",
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&p->config.sense_bitfield_width);
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p->config.control_parent = of_property_read_bool(dev->of_node,
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"control-parent");
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}
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if (!p->config.sense_bitfield_width)
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p->config.sense_bitfield_width = 4; /* default to 4 bits */
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&p->sense_bitfield_width);
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control_parent = of_property_read_bool(dev->of_node, "control-parent");
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if (!p->sense_bitfield_width)
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p->sense_bitfield_width = 4; /* default to 4 bits */
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p->pdev = pdev;
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platform_set_drvdata(pdev, p);
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of_id = of_match_device(intc_irqpin_dt_ids, dev);
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if (of_id && of_id->data) {
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config = of_id->data;
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p->needs_clk = config->needs_clk;
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}
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p->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(p->clk)) {
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dev_warn(dev, "unable to get clock\n");
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if (p->needs_clk) {
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dev_err(dev, "unable to get clock\n");
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ret = PTR_ERR(p->clk);
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goto err0;
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}
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p->clk = NULL;
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}
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@ -443,8 +462,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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p->irq[k].requested_irq = irq->start;
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}
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p->number_of_irqs = k;
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if (p->number_of_irqs < 1) {
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nirqs = k;
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if (nirqs < 1) {
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dev_err(dev, "not enough IRQ resources\n");
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ret = -EINVAL;
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goto err0;
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@ -485,20 +504,16 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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}
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/* configure "individual IRQ mode" where needed */
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of_id = of_match_device(intc_irqpin_dt_ids, dev);
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if (of_id && of_id->data) {
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const struct intc_irqpin_irlm_config *irlm_config = of_id->data;
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if (config && config->needs_irlm) {
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if (io[INTC_IRQPIN_REG_IRLM])
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intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
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irlm_config->irlm_bit,
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1, 1);
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config->irlm_bit, 1, 1);
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else
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dev_warn(dev, "unable to select IRLM mode\n");
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}
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/* mask all interrupts using priority */
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for (k = 0; k < p->number_of_irqs; k++)
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for (k = 0; k < nirqs; k++)
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intc_irqpin_mask_unmask_prio(p, k, 1);
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/* clear all pending interrupts */
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@ -506,16 +521,16 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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/* scan for shared interrupt lines */
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ref_irq = p->irq[0].requested_irq;
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p->shared_irqs = true;
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for (k = 1; k < p->number_of_irqs; k++) {
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p->shared_irqs = 1;
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for (k = 1; k < nirqs; k++) {
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if (ref_irq != p->irq[k].requested_irq) {
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p->shared_irqs = false;
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p->shared_irqs = 0;
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break;
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}
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}
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/* use more severe masking method if requested */
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if (p->config.control_parent) {
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if (control_parent) {
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enable_fn = intc_irqpin_irq_enable_force;
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disable_fn = intc_irqpin_irq_disable_force;
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} else if (!p->shared_irqs) {
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@ -534,9 +549,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
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irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
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p->irq_domain = irq_domain_add_simple(dev->of_node,
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p->number_of_irqs,
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p->config.irq_base,
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p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
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&intc_irqpin_irq_domain_ops, p);
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if (!p->irq_domain) {
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ret = -ENXIO;
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@ -555,7 +568,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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}
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} else {
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/* request interrupts one by one */
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for (k = 0; k < p->number_of_irqs; k++) {
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for (k = 0; k < nirqs; k++) {
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if (devm_request_irq(dev, p->irq[k].requested_irq,
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intc_irqpin_irq_handler, 0, name,
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&p->irq[k])) {
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@ -567,17 +580,10 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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}
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/* unmask all interrupts on prio level */
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for (k = 0; k < p->number_of_irqs; k++)
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for (k = 0; k < nirqs; k++)
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intc_irqpin_mask_unmask_prio(p, k, 0);
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dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
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/* warn in case of mismatch if irq base is specified */
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if (p->config.irq_base) {
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if (p->config.irq_base != p->irq[0].domain_irq)
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dev_warn(dev, "irq base mismatch (%d/%d)\n",
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p->config.irq_base, p->irq[0].domain_irq);
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}
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dev_info(dev, "driving %d irqs\n", nirqs);
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return 0;
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@ -50,6 +50,12 @@ static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
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.enable = 0x34,
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};
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static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
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.ctrl = 0x00,
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.pend = 0x08,
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.enable = 0x04,
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};
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static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
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u32 val)
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{
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@ -207,3 +213,10 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
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return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
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}
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IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
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static int __init sun9i_nmi_irq_init(struct device_node *node,
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struct device_node *parent)
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{
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return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
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}
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IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
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@ -1,29 +0,0 @@
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/*
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* Renesas INTC External IRQ Pin Driver
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*
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__
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#define __IRQ_RENESAS_INTC_IRQPIN_H__
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struct renesas_intc_irqpin_config {
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unsigned int sense_bitfield_width;
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unsigned int irq_base;
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bool control_parent;
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};
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#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */
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