i2c: i801: convert to use common P2SB accessor
Since we have a common P2SB accessor in tree we may use it instead of open coded variants. Replace custom code by p2sb_bar() call. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Henning Schild <henning.schild@siemens.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Jean Delvare <jdelvare@suse.de> Acked-by: Wolfram Sang <wsa@kernel.org> Signed-off-by: Lee Jones <lee@kernel.org>
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@ -108,6 +108,7 @@ config I2C_HIX5HD2
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config I2C_I801
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tristate "Intel 82801 (ICH/PCH)"
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depends on PCI
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select P2SB if X86
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select CHECK_SIGNATURE if X86 && DMI
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select I2C_SMBUS
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help
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@ -111,6 +111,7 @@
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/itco_wdt.h>
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#include <linux/platform_data/x86/p2sb.h>
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#include <linux/pm_runtime.h>
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#include <linux/mutex.h>
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@ -140,7 +141,6 @@
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#define TCOBASE 0x050
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#define TCOCTL 0x054
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#define SBREG_BAR 0x10
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#define SBREG_SMBCTRL 0xc6000c
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#define SBREG_SMBCTRL_DNV 0xcf000c
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@ -1482,45 +1482,24 @@ i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
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.version = 4,
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};
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struct resource *res;
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unsigned int devfn;
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u64 base64_addr;
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u32 base_addr;
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u8 hidden;
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int ret;
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/*
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* We must access the NO_REBOOT bit over the Primary to Sideband
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* bridge (P2SB). The BIOS prevents the P2SB device from being
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* enumerated by the PCI subsystem, so we need to unhide/hide it
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* to lookup the P2SB BAR.
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* (P2SB) bridge.
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*/
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pci_lock_rescan_remove();
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devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
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/* Unhide the P2SB device, if it is hidden */
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pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
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if (hidden)
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pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
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pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
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base64_addr = base_addr & 0xfffffff0;
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pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
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base64_addr |= (u64)base_addr << 32;
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/* Hide the P2SB device, if it was hidden before */
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if (hidden)
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pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
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pci_unlock_rescan_remove();
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res = &tco_res[1];
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ret = p2sb_bar(pci_dev->bus, 0, res);
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if (ret)
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return ERR_PTR(ret);
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if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
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res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
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res->start += SBREG_SMBCTRL_DNV;
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else
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res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
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res->start += SBREG_SMBCTRL;
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res->end = res->start + 3;
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res->flags = IORESOURCE_MEM;
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return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
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tco_res, 2, &pldata, sizeof(pldata));
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@ -21,6 +21,12 @@
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static const struct x86_cpu_id p2sb_cpu_ids[] = {
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, PCI_DEVFN(31, 1)),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, PCI_DEVFN(31, 1)),
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X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, PCI_DEVFN(31, 1)),
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X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, PCI_DEVFN(31, 1)),
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X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, PCI_DEVFN(31, 1)),
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X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, PCI_DEVFN(31, 1)),
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{}
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};
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