Merge branch 'hns3-next'
Huazhong Tan says: ==================== net: hns3: add some misc update about reset issue This series includes some misc update relating to reset issue. [patch 1/7] & [patch 2/7] splits hclge_reset()/hclgevf_reset() into two parts: preparing and rebuilding. Since the procedure of FLR should be separated out from the reset task([patch 3/7 & patch 3/7]), then the FLR's processing can reuse these codes. pci_error_handlers.reset_prepare() is void type function, so [patch 6/7] & [patch 7/7] factor some codes related to PF function reset to make the preparing done before .reset_prepare() return. BTW, [patch 5/7] enlarges the waiting time of reset for matching the hardware's. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
5c9166f038
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@ -167,11 +167,6 @@ enum hnae3_reset_type {
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HNAE3_MAX_RESET,
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};
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enum hnae3_flr_state {
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HNAE3_FLR_DOWN,
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HNAE3_FLR_DONE,
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};
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enum hnae3_port_base_vlan_state {
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HNAE3_PORT_BASE_VLAN_DISABLE,
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HNAE3_PORT_BASE_VLAN_ENABLE,
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@ -3260,7 +3260,8 @@ static int hclge_notify_roce_client(struct hclge_dev *hdev,
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static int hclge_reset_wait(struct hclge_dev *hdev)
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{
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#define HCLGE_RESET_WATI_MS 100
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#define HCLGE_RESET_WAIT_CNT 200
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#define HCLGE_RESET_WAIT_CNT 350
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u32 val, reg, reg_bit;
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u32 cnt = 0;
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@ -3277,8 +3278,6 @@ static int hclge_reset_wait(struct hclge_dev *hdev)
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reg = HCLGE_FUN_RST_ING;
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reg_bit = HCLGE_FUN_RST_ING_B;
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break;
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case HNAE3_FLR_RESET:
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break;
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default:
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dev_err(&hdev->pdev->dev,
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"Wait for unsupported reset type: %d\n",
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@ -3286,20 +3285,6 @@ static int hclge_reset_wait(struct hclge_dev *hdev)
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return -EINVAL;
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}
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if (hdev->reset_type == HNAE3_FLR_RESET) {
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while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
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cnt++ < HCLGE_RESET_WAIT_CNT)
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msleep(HCLGE_RESET_WATI_MS);
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if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
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dev_err(&hdev->pdev->dev,
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"flr wait timeout: %u\n", cnt);
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return -EBUSY;
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}
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return 0;
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}
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val = hclge_read_dev(&hdev->hw, reg);
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while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
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msleep(HCLGE_RESET_WATI_MS);
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@ -3377,7 +3362,7 @@ static void hclge_mailbox_service_task(struct hclge_dev *hdev)
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clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
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}
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static int hclge_func_reset_sync_vf(struct hclge_dev *hdev)
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static void hclge_func_reset_sync_vf(struct hclge_dev *hdev)
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{
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struct hclge_pf_rst_sync_cmd *req;
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struct hclge_desc desc;
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@ -3397,20 +3382,19 @@ static int hclge_func_reset_sync_vf(struct hclge_dev *hdev)
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*/
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if (ret == -EOPNOTSUPP) {
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msleep(HCLGE_RESET_SYNC_TIME);
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return 0;
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return;
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} else if (ret) {
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dev_err(&hdev->pdev->dev, "sync with VF fail %d!\n",
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ret);
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return ret;
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dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n",
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ret);
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return;
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} else if (req->all_vf_ready) {
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return 0;
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return;
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}
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msleep(HCLGE_PF_RESET_SYNC_TIME);
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hclge_cmd_reuse_desc(&desc, true);
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} while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
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dev_err(&hdev->pdev->dev, "sync with VF timeout!\n");
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return -ETIME;
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dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
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}
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void hclge_report_hw_error(struct hclge_dev *hdev,
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@ -3490,12 +3474,6 @@ static void hclge_do_reset(struct hclge_dev *hdev)
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set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
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hclge_reset_task_schedule(hdev);
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break;
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case HNAE3_FLR_RESET:
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dev_info(&pdev->dev, "FLR requested\n");
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/* schedule again to check later */
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set_bit(HNAE3_FLR_RESET, &hdev->reset_pending);
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hclge_reset_task_schedule(hdev);
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break;
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default:
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dev_warn(&pdev->dev,
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"Unsupported reset type: %d\n", hdev->reset_type);
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@ -3584,23 +3562,6 @@ static void hclge_clear_reset_cause(struct hclge_dev *hdev)
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hclge_enable_vector(&hdev->misc_vector, true);
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}
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static int hclge_reset_prepare_down(struct hclge_dev *hdev)
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{
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int ret = 0;
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switch (hdev->reset_type) {
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case HNAE3_FUNC_RESET:
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/* fall through */
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case HNAE3_FLR_RESET:
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ret = hclge_set_all_vf_rst(hdev, true);
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break;
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default:
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break;
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}
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return ret;
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}
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static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
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{
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u32 reg_val;
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@ -3614,6 +3575,19 @@ static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
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hclge_write_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG, reg_val);
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}
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static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
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{
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int ret;
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ret = hclge_set_all_vf_rst(hdev, true);
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if (ret)
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return ret;
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hclge_func_reset_sync_vf(hdev);
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return 0;
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}
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static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
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{
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u32 reg_val;
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@ -3621,10 +3595,7 @@ static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
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switch (hdev->reset_type) {
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case HNAE3_FUNC_RESET:
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/* to confirm whether all running VF is ready
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* before request PF reset
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*/
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ret = hclge_func_reset_sync_vf(hdev);
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ret = hclge_func_reset_notify_vf(hdev);
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if (ret)
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return ret;
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@ -3644,16 +3615,9 @@ static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
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hdev->rst_stats.pf_rst_cnt++;
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break;
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case HNAE3_FLR_RESET:
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/* to confirm whether all running VF is ready
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* before request PF reset
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*/
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ret = hclge_func_reset_sync_vf(hdev);
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ret = hclge_func_reset_notify_vf(hdev);
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if (ret)
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return ret;
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set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
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set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
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hdev->rst_stats.flr_rst_cnt++;
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break;
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case HNAE3_IMP_RESET:
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hclge_handle_imp_error(hdev);
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@ -3782,10 +3746,9 @@ static int hclge_reset_stack(struct hclge_dev *hdev)
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return hclge_notify_client(hdev, HNAE3_RESTORE_CLIENT);
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}
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static void hclge_reset(struct hclge_dev *hdev)
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static int hclge_reset_prepare(struct hclge_dev *hdev)
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{
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struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
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enum hnae3_reset_type reset_level;
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int ret;
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/* Initialize ae_dev reset status as well, in case enet layer wants to
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@ -3796,45 +3759,41 @@ static void hclge_reset(struct hclge_dev *hdev)
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/* perform reset of the stack & ae device for a client */
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ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
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if (ret)
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goto err_reset;
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ret = hclge_reset_prepare_down(hdev);
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if (ret)
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goto err_reset;
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return ret;
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rtnl_lock();
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ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
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if (ret)
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goto err_reset_lock;
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rtnl_unlock();
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ret = hclge_reset_prepare_wait(hdev);
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if (ret)
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goto err_reset;
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return ret;
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if (hclge_reset_wait(hdev))
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goto err_reset;
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return hclge_reset_prepare_wait(hdev);
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}
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static int hclge_reset_rebuild(struct hclge_dev *hdev)
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{
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struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
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enum hnae3_reset_type reset_level;
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int ret;
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hdev->rst_stats.hw_reset_done_cnt++;
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ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
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if (ret)
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goto err_reset;
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return ret;
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rtnl_lock();
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ret = hclge_reset_stack(hdev);
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rtnl_unlock();
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if (ret)
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goto err_reset_lock;
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return ret;
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hclge_clear_reset_cause(hdev);
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ret = hclge_reset_prepare_up(hdev);
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if (ret)
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goto err_reset_lock;
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return ret;
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rtnl_unlock();
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ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
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/* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1
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@ -3842,19 +3801,17 @@ static void hclge_reset(struct hclge_dev *hdev)
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*/
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if (ret &&
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hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1)
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goto err_reset;
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return ret;
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rtnl_lock();
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ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
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if (ret)
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goto err_reset_lock;
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rtnl_unlock();
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if (ret)
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return ret;
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ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
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if (ret)
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goto err_reset;
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return ret;
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hdev->last_reset_time = jiffies;
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hdev->rst_stats.reset_fail_cnt = 0;
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@ -3871,10 +3828,22 @@ static void hclge_reset(struct hclge_dev *hdev)
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if (reset_level != HNAE3_NONE_RESET)
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set_bit(reset_level, &hdev->reset_request);
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return 0;
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}
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static void hclge_reset(struct hclge_dev *hdev)
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{
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if (hclge_reset_prepare(hdev))
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goto err_reset;
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if (hclge_reset_wait(hdev))
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goto err_reset;
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if (hclge_reset_rebuild(hdev))
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goto err_reset;
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return;
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err_reset_lock:
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rtnl_unlock();
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err_reset:
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if (hclge_reset_err_handle(hdev))
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hclge_reset_task_schedule(hdev);
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@ -3980,12 +3949,13 @@ static void hclge_reset_service_task(struct hclge_dev *hdev)
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if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
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return;
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if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
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return;
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down(&hdev->reset_sem);
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set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
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hclge_reset_subtask(hdev);
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clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
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up(&hdev->reset_sem);
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}
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static void hclge_update_vport_alive(struct hclge_dev *hdev)
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|
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@ -9332,30 +9302,53 @@ static void hclge_state_uninit(struct hclge_dev *hdev)
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|
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static void hclge_flr_prepare(struct hnae3_ae_dev *ae_dev)
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{
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#define HCLGE_FLR_WAIT_MS 100
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#define HCLGE_FLR_WAIT_CNT 50
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#define HCLGE_FLR_RETRY_WAIT_MS 500
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#define HCLGE_FLR_RETRY_CNT 5
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struct hclge_dev *hdev = ae_dev->priv;
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int cnt = 0;
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int retry_cnt = 0;
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int ret;
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clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
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clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
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set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
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hclge_reset_event(hdev->pdev, NULL);
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retry:
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down(&hdev->reset_sem);
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set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
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hdev->reset_type = HNAE3_FLR_RESET;
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ret = hclge_reset_prepare(hdev);
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if (ret) {
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dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n",
|
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ret);
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if (hdev->reset_pending ||
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retry_cnt++ < HCLGE_FLR_RETRY_CNT) {
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dev_err(&hdev->pdev->dev,
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"reset_pending:0x%lx, retry_cnt:%d\n",
|
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hdev->reset_pending, retry_cnt);
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clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
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up(&hdev->reset_sem);
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msleep(HCLGE_FLR_RETRY_WAIT_MS);
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goto retry;
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}
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}
|
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|
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while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
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cnt++ < HCLGE_FLR_WAIT_CNT)
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msleep(HCLGE_FLR_WAIT_MS);
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|
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if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
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dev_err(&hdev->pdev->dev,
|
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"flr wait down timeout: %d\n", cnt);
|
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/* disable misc vector before FLR done */
|
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hclge_enable_vector(&hdev->misc_vector, false);
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set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
|
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hdev->rst_stats.flr_rst_cnt++;
|
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}
|
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|
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static void hclge_flr_done(struct hnae3_ae_dev *ae_dev)
|
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{
|
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struct hclge_dev *hdev = ae_dev->priv;
|
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int ret;
|
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|
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set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
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hclge_enable_vector(&hdev->misc_vector, true);
|
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|
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ret = hclge_reset_rebuild(hdev);
|
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if (ret)
|
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dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret);
|
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|
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hdev->reset_type = HNAE3_NONE_RESET;
|
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clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
|
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up(&hdev->reset_sem);
|
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}
|
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|
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static void hclge_clear_resetting_state(struct hclge_dev *hdev)
|
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|
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@ -9398,6 +9391,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
|
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|
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mutex_init(&hdev->vport_lock);
|
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spin_lock_init(&hdev->fd_rule_lock);
|
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sema_init(&hdev->reset_sem, 1);
|
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|
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ret = hclge_pci_init(hdev);
|
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if (ret) {
|
||||
|
|
|
|||
|
|
@ -720,6 +720,7 @@ struct hclge_dev {
|
|||
unsigned long reset_request; /* reset has been requested */
|
||||
unsigned long reset_pending; /* client rst is pending to be served */
|
||||
struct hclge_rst_stats rst_stats;
|
||||
struct semaphore reset_sem; /* protect reset process */
|
||||
u32 fw_version;
|
||||
u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
|
||||
u16 num_tqps; /* Num task queue pairs of this PF */
|
||||
|
|
|
|||
|
|
@ -1411,32 +1411,6 @@ static int hclgevf_notify_client(struct hclgevf_dev *hdev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev)
|
||||
{
|
||||
struct hclgevf_dev *hdev = ae_dev->priv;
|
||||
|
||||
set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
|
||||
}
|
||||
|
||||
static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev,
|
||||
unsigned long delay_us,
|
||||
unsigned long wait_cnt)
|
||||
{
|
||||
unsigned long cnt = 0;
|
||||
|
||||
while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
|
||||
cnt++ < wait_cnt)
|
||||
usleep_range(delay_us, delay_us * 2);
|
||||
|
||||
if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"flr wait timeout\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
|
||||
{
|
||||
#define HCLGEVF_RESET_WAIT_US 20000
|
||||
|
|
@ -1447,11 +1421,7 @@ static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
|
|||
u32 val;
|
||||
int ret;
|
||||
|
||||
if (hdev->reset_type == HNAE3_FLR_RESET)
|
||||
return hclgevf_flr_poll_timeout(hdev,
|
||||
HCLGEVF_RESET_WAIT_US,
|
||||
HCLGEVF_RESET_WAIT_CNT);
|
||||
else if (hdev->reset_type == HNAE3_VF_RESET)
|
||||
if (hdev->reset_type == HNAE3_VF_RESET)
|
||||
ret = readl_poll_timeout(hdev->hw.io_base +
|
||||
HCLGEVF_VF_RST_ING, val,
|
||||
!(val & HCLGEVF_VF_RST_ING_BIT),
|
||||
|
|
@ -1523,7 +1493,8 @@ static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
|
|||
/* clear handshake status with IMP */
|
||||
hclgevf_reset_handshake(hdev, false);
|
||||
|
||||
return 0;
|
||||
/* bring up the nic to enable TX/RX again */
|
||||
return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
|
||||
}
|
||||
|
||||
static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
|
||||
|
|
@ -1532,18 +1503,10 @@ static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
|
|||
|
||||
int ret = 0;
|
||||
|
||||
switch (hdev->reset_type) {
|
||||
case HNAE3_VF_FUNC_RESET:
|
||||
if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
|
||||
ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
|
||||
0, true, NULL, sizeof(u8));
|
||||
hdev->rst_stats.vf_func_rst_cnt++;
|
||||
break;
|
||||
case HNAE3_FLR_RESET:
|
||||
set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
|
||||
hdev->rst_stats.flr_rst_cnt++;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
|
||||
|
|
@ -1603,7 +1566,7 @@ static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
|
|||
}
|
||||
}
|
||||
|
||||
static int hclgevf_reset(struct hclgevf_dev *hdev)
|
||||
static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
|
||||
{
|
||||
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
|
||||
int ret;
|
||||
|
|
@ -1613,62 +1576,64 @@ static int hclgevf_reset(struct hclgevf_dev *hdev)
|
|||
*/
|
||||
ae_dev->reset_type = hdev->reset_type;
|
||||
hdev->rst_stats.rst_cnt++;
|
||||
rtnl_lock();
|
||||
|
||||
rtnl_lock();
|
||||
/* bring down the nic to stop any ongoing TX/RX */
|
||||
ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
|
||||
if (ret)
|
||||
goto err_reset_lock;
|
||||
|
||||
rtnl_unlock();
|
||||
|
||||
ret = hclgevf_reset_prepare_wait(hdev);
|
||||
if (ret)
|
||||
goto err_reset;
|
||||
return ret;
|
||||
|
||||
/* check if VF could successfully fetch the hardware reset completion
|
||||
* status from the hardware
|
||||
*/
|
||||
ret = hclgevf_reset_wait(hdev);
|
||||
if (ret) {
|
||||
/* can't do much in this situation, will disable VF */
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"VF failed(=%d) to fetch H/W reset completion status\n",
|
||||
ret);
|
||||
goto err_reset;
|
||||
}
|
||||
return hclgevf_reset_prepare_wait(hdev);
|
||||
}
|
||||
|
||||
static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
|
||||
{
|
||||
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
|
||||
int ret;
|
||||
|
||||
hdev->rst_stats.hw_rst_done_cnt++;
|
||||
|
||||
rtnl_lock();
|
||||
|
||||
/* now, re-initialize the nic client and ae device */
|
||||
ret = hclgevf_reset_stack(hdev);
|
||||
rtnl_unlock();
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
|
||||
goto err_reset_lock;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* bring up the nic to enable TX/RX again */
|
||||
ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
|
||||
if (ret)
|
||||
goto err_reset_lock;
|
||||
|
||||
rtnl_unlock();
|
||||
|
||||
hdev->last_reset_time = jiffies;
|
||||
ae_dev->reset_type = HNAE3_NONE_RESET;
|
||||
hdev->rst_stats.rst_done_cnt++;
|
||||
hdev->rst_stats.rst_fail_cnt = 0;
|
||||
clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
|
||||
|
||||
return ret;
|
||||
err_reset_lock:
|
||||
rtnl_unlock();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hclgevf_reset(struct hclgevf_dev *hdev)
|
||||
{
|
||||
if (hclgevf_reset_prepare(hdev))
|
||||
goto err_reset;
|
||||
|
||||
/* check if VF could successfully fetch the hardware reset completion
|
||||
* status from the hardware
|
||||
*/
|
||||
if (hclgevf_reset_wait(hdev)) {
|
||||
/* can't do much in this situation, will disable VF */
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"failed to fetch H/W reset completion status\n");
|
||||
goto err_reset;
|
||||
}
|
||||
|
||||
if (hclgevf_reset_rebuild(hdev))
|
||||
goto err_reset;
|
||||
|
||||
return;
|
||||
|
||||
err_reset:
|
||||
hclgevf_reset_err_handle(hdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
|
||||
|
|
@ -1731,25 +1696,60 @@ static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
|
|||
set_bit(rst_type, &hdev->default_reset_request);
|
||||
}
|
||||
|
||||
static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
|
||||
{
|
||||
writel(en ? 1 : 0, vector->addr);
|
||||
}
|
||||
|
||||
static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev)
|
||||
{
|
||||
#define HCLGEVF_FLR_WAIT_MS 100
|
||||
#define HCLGEVF_FLR_WAIT_CNT 50
|
||||
#define HCLGEVF_FLR_RETRY_WAIT_MS 500
|
||||
#define HCLGEVF_FLR_RETRY_CNT 5
|
||||
|
||||
struct hclgevf_dev *hdev = ae_dev->priv;
|
||||
int cnt = 0;
|
||||
int retry_cnt = 0;
|
||||
int ret;
|
||||
|
||||
clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
|
||||
clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
|
||||
set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
|
||||
hclgevf_reset_event(hdev->pdev, NULL);
|
||||
retry:
|
||||
down(&hdev->reset_sem);
|
||||
set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
|
||||
hdev->reset_type = HNAE3_FLR_RESET;
|
||||
ret = hclgevf_reset_prepare(hdev);
|
||||
if (ret) {
|
||||
dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n",
|
||||
ret);
|
||||
if (hdev->reset_pending ||
|
||||
retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) {
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"reset_pending:0x%lx, retry_cnt:%d\n",
|
||||
hdev->reset_pending, retry_cnt);
|
||||
clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
|
||||
up(&hdev->reset_sem);
|
||||
msleep(HCLGEVF_FLR_RETRY_WAIT_MS);
|
||||
goto retry;
|
||||
}
|
||||
}
|
||||
|
||||
while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
|
||||
cnt++ < HCLGEVF_FLR_WAIT_CNT)
|
||||
msleep(HCLGEVF_FLR_WAIT_MS);
|
||||
/* disable misc vector before FLR done */
|
||||
hclgevf_enable_vector(&hdev->misc_vector, false);
|
||||
hdev->rst_stats.flr_rst_cnt++;
|
||||
}
|
||||
|
||||
if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"flr wait down timeout: %d\n", cnt);
|
||||
static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev)
|
||||
{
|
||||
struct hclgevf_dev *hdev = ae_dev->priv;
|
||||
int ret;
|
||||
|
||||
hclgevf_enable_vector(&hdev->misc_vector, true);
|
||||
|
||||
ret = hclgevf_reset_rebuild(hdev);
|
||||
if (ret)
|
||||
dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
|
||||
ret);
|
||||
|
||||
hdev->reset_type = HNAE3_NONE_RESET;
|
||||
clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
|
||||
up(&hdev->reset_sem);
|
||||
}
|
||||
|
||||
static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
|
||||
|
|
@ -1802,13 +1802,11 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
|
|||
{
|
||||
#define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3
|
||||
|
||||
int ret;
|
||||
|
||||
if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
|
||||
return;
|
||||
|
||||
if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
|
||||
return;
|
||||
down(&hdev->reset_sem);
|
||||
set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
|
||||
|
||||
if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
|
||||
&hdev->reset_state)) {
|
||||
|
|
@ -1822,12 +1820,8 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
|
|||
hdev->last_reset_time = jiffies;
|
||||
while ((hdev->reset_type =
|
||||
hclgevf_get_reset_level(hdev, &hdev->reset_pending))
|
||||
!= HNAE3_NONE_RESET) {
|
||||
ret = hclgevf_reset(hdev);
|
||||
if (ret)
|
||||
dev_err(&hdev->pdev->dev,
|
||||
"VF stack reset failed %d.\n", ret);
|
||||
}
|
||||
!= HNAE3_NONE_RESET)
|
||||
hclgevf_reset(hdev);
|
||||
} else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
|
||||
&hdev->reset_state)) {
|
||||
/* we could be here when either of below happens:
|
||||
|
|
@ -1869,6 +1863,7 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
|
|||
}
|
||||
|
||||
clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
|
||||
up(&hdev->reset_sem);
|
||||
}
|
||||
|
||||
static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
|
||||
|
|
@ -2012,11 +2007,6 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
|
|||
return HCLGEVF_VECTOR0_EVENT_OTHER;
|
||||
}
|
||||
|
||||
static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
|
||||
{
|
||||
writel(en ? 1 : 0, vector->addr);
|
||||
}
|
||||
|
||||
static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
|
||||
{
|
||||
enum hclgevf_evt_cause event_cause;
|
||||
|
|
@ -2291,6 +2281,7 @@ static void hclgevf_state_init(struct hclgevf_dev *hdev)
|
|||
INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
|
||||
|
||||
mutex_init(&hdev->mbx_resp.mbx_mutex);
|
||||
sema_init(&hdev->reset_sem, 1);
|
||||
|
||||
/* bring the device down */
|
||||
set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
|
||||
|
|
|
|||
|
|
@ -253,6 +253,7 @@ struct hclgevf_dev {
|
|||
unsigned long reset_state; /* requested, pending */
|
||||
struct hclgevf_rst_stats rst_stats;
|
||||
u32 reset_attempts;
|
||||
struct semaphore reset_sem; /* protect reset process */
|
||||
|
||||
u32 fw_version;
|
||||
u16 num_tqps; /* num task queue pairs of this PF */
|
||||
|
|
|
|||
Загрузка…
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