ARM64: Add new Xilinx ZynqMP SoC
Initial version of device tree for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Michal Simek
Arnd Bergmann
Родитель
13a7a6ac0a
Коммит
5d1b79d2b2
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@ -228,6 +228,11 @@ config ARCH_XGENE
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_ZYNQMP
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bool "Xilinx ZynqMP Family"
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help
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This enables support for Xilinx ZynqMP Family
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endmenu
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menu "Bus support"
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@ -5,5 +5,6 @@ dts-dirs += cavium
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dts-dirs += exynos
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dts-dirs += freescale
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dts-dirs += mediatek
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dts-dirs += xilinx
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subdir-y := $(dts-dirs)
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@ -0,0 +1,5 @@
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb
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@ -0,0 +1,47 @@
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/*
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* dts file for Xilinx ZynqMP ep108 development board
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*
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* (C) Copyright 2014 - 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/dts-v1/;
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/include/ "zynqmp.dtsi"
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/ {
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model = "ZynqMP EP108";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x40000000>;
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};
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};
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: phy@0{
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reg = <0>;
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max-speed = <100>;
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -0,0 +1,305 @@
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/*
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* dts file for Xilinx ZynqMP
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*
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* (C) Copyright 2014 - 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/ {
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compatible = "xlnx,zynqmp";
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#address-cells = <2>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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enable-method = "psci";
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reg = <0x3>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 143 4>,
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<0 144 4>,
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<0 145 4>,
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<0 146 4>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <1 13 0xf01>,
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<1 14 0xf01>,
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<1 11 0xf01>,
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<1 10 0xf01>;
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};
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amba_apu {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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reg = <0x0 0xf9010000 0x10000>,
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<0x0 0xf902f000 0x2000>,
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<0x0 0xf9040000 0x20000>,
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<0x0 0xf906f000 0x2000>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <1 9 0xf04>;
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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misc_clk: misc_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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ttc0: timer@ff110000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
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reg = <0x0 0xff110000 0x1000>;
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clocks = <&misc_clk>;
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timer-width = <32>;
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};
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ttc1: timer@ff120000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
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reg = <0x0 0xff120000 0x1000>;
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clocks = <&misc_clk>;
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timer-width = <32>;
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};
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ttc2: timer@ff130000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
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reg = <0x0 0xff130000 0x1000>;
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clocks = <&misc_clk>;
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timer-width = <32>;
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};
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ttc3: timer@ff140000 {
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compatible = "cdns,ttc";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
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reg = <0x0 0xff140000 0x1000>;
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clocks = <&misc_clk>;
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timer-width = <32>;
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};
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uart0: serial@ff000000 {
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compatible = "cdns,uart-r1p8";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 21 4>;
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reg = <0x0 0xff000000 0x1000>;
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clock-names = "uart_clk", "pclk";
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clocks = <&misc_clk &misc_clk>;
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};
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uart1: serial@ff010000 {
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compatible = "cdns,uart-r1p8";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 22 4>;
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reg = <0x0 0xff010000 0x1000>;
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clock-names = "uart_clk", "pclk";
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clocks = <&misc_clk &misc_clk>;
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};
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gpio: gpio@ff0a0000 {
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compatible = "xlnx,zynq-gpio-1.0";
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status = "disabled";
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#gpio-cells = <0x2>;
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clocks = <&misc_clk>;
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interrupt-parent = <&gic>;
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interrupts = <0 16 4>;
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reg = <0x0 0xff0a0000 0x1000>;
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};
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gem0: ethernet@ff0b0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 57 4>, <0 57 4>;
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reg = <0x0 0xff0b0000 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem1: ethernet@ff0c0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 59 4>, <0 59 4>;
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reg = <0x0 0xff0c0000 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem2: ethernet@ff0d0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 61 4>, <0 61 4>;
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reg = <0x0 0xff0d0000 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gem3: ethernet@ff0e0000 {
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compatible = "cdns,gem";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 63 4>, <0 63 4>;
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reg = <0x0 0xff0e0000 0x1000>;
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clock-names = "pclk", "hclk", "tx_clk";
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clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@ff040000 {
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compatible = "cdns,spi-r1p6";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 19 4>;
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reg = <0x0 0xff040000 0x1000>;
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clock-names = "ref_clk", "pclk";
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clocks = <&misc_clk &misc_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@ff050000 {
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compatible = "cdns,spi-r1p6";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 20 4>;
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reg = <0x0 0xff050000 0x1000>;
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clock-names = "ref_clk", "pclk";
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clocks = <&misc_clk &misc_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c_clk: i2c_clk {
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compatible = "fixed-clock";
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#clock-cells = <0x0>;
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clock-frequency = <111111111>;
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};
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i2c0: i2c@ff020000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 17 4>;
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reg = <0x0 0xff020000 0x1000>;
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clocks = <&i2c_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@ff030000 {
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compatible = "cdns,i2c-r1p10";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 18 4>;
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reg = <0x0 0xff030000 0x1000>;
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clocks = <&i2c_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sdhci0: sdhci@ff160000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 48 4>;
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reg = <0x0 0xff160000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&misc_clk>, <&misc_clk>;
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};
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sdhci1: sdhci@ff170000 {
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compatible = "arasan,sdhci-8.9a";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <0 49 4>;
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reg = <0x0 0xff170000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&misc_clk>, <&misc_clk>;
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};
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watchdog0: watchdog@fd4d0000 {
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compatible = "cdns,wdt-r1p2";
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status = "disabled";
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clocks= <&misc_clk>;
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interrupt-parent = <&gic>;
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interrupts = <0 52 1>;
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reg = <0x0 0xfd4d0000 0x1000>;
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timeout-sec = <10>;
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};
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};
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};
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@ -36,6 +36,7 @@ CONFIG_ARCH_MEDIATEK=y
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CONFIG_ARCH_THUNDER=y
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CONFIG_ARCH_VEXPRESS=y
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CONFIG_ARCH_XGENE=y
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CONFIG_ARCH_ZYNQMP=y
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CONFIG_PCI=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_XGENE=y
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@ -94,6 +95,8 @@ CONFIG_SERIAL_8250_MT6577=y
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CONFIG_SERIAL_AMBA_PL011=y
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CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
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CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_SERIAL_XILINX_PS_UART=y
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CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
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CONFIG_VIRTIO_CONSOLE=y
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# CONFIG_HW_RANDOM is not set
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CONFIG_SPI=y
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