mtd: rawnand: ingenic: Convert the driver to exec_op()
Let's convert the driver to exec_op() to have one less driver relying on the legacy interface. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Tested-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200519232454.374081-4-boris.brezillon@collabora.com
This commit is contained in:
Boris Brezillon
Miquel Raynal
Родитель
2e26301101
Коммит
5d55714fa5
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@ -27,9 +27,6 @@
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#define DRV_NAME "ingenic-nand"
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/* Command delay when there is no R/B pin. */
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#define RB_DELAY_US 100
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struct jz_soc_info {
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unsigned long data_offset;
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unsigned long addr_offset;
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@ -49,7 +46,6 @@ struct ingenic_nfc {
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struct nand_controller controller;
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unsigned int num_banks;
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struct list_head chips;
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int selected;
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struct ingenic_nand_cs cs[];
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};
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@ -142,51 +138,6 @@ static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
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.free = jz4725b_ooblayout_free,
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};
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static void ingenic_nand_select_chip(struct nand_chip *chip, int chipnr)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
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struct ingenic_nand_cs *cs;
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/* Ensure the currently selected chip is deasserted. */
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if (chipnr == -1 && nfc->selected >= 0) {
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cs = &nfc->cs[nfc->selected];
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jz4780_nemc_assert(nfc->dev, cs->bank, false);
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}
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nfc->selected = chipnr;
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}
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static void ingenic_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
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unsigned int ctrl)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
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struct ingenic_nand_cs *cs;
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if (WARN_ON(nfc->selected < 0))
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return;
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cs = &nfc->cs[nfc->selected];
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jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_ALE)
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writeb(cmd, cs->base + nfc->soc_info->addr_offset);
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else if (ctrl & NAND_CLE)
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writeb(cmd, cs->base + nfc->soc_info->cmd_offset);
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}
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static int ingenic_nand_dev_ready(struct nand_chip *chip)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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return gpiod_get_value_cansleep(nand->busy_gpio);
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}
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static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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@ -298,8 +249,91 @@ static int ingenic_nand_attach_chip(struct nand_chip *chip)
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return 0;
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}
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static int ingenic_nand_exec_instr(struct nand_chip *chip,
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struct ingenic_nand_cs *cs,
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const struct nand_op_instr *instr)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
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unsigned int i;
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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writeb(instr->ctx.cmd.opcode,
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cs->base + nfc->soc_info->cmd_offset);
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return 0;
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case NAND_OP_ADDR_INSTR:
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for (i = 0; i < instr->ctx.addr.naddrs; i++)
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writeb(instr->ctx.addr.addrs[i],
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cs->base + nfc->soc_info->addr_offset);
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return 0;
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case NAND_OP_DATA_IN_INSTR:
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if (instr->ctx.data.force_8bit ||
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!(chip->options & NAND_BUSWIDTH_16))
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ioread8_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.in,
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instr->ctx.data.len);
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else
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ioread16_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.in,
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instr->ctx.data.len);
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return 0;
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case NAND_OP_DATA_OUT_INSTR:
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if (instr->ctx.data.force_8bit ||
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!(chip->options & NAND_BUSWIDTH_16))
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iowrite8_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.out,
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instr->ctx.data.len);
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else
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iowrite16_rep(cs->base + nfc->soc_info->data_offset,
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instr->ctx.data.buf.out,
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instr->ctx.data.len);
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return 0;
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case NAND_OP_WAITRDY_INSTR:
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if (!nand->busy_gpio)
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return nand_soft_waitrdy(chip,
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instr->ctx.waitrdy.timeout_ms);
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return nand_gpio_waitrdy(chip, nand->busy_gpio,
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instr->ctx.waitrdy.timeout_ms);
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default:
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break;
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}
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return -EINVAL;
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}
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static int ingenic_nand_exec_op(struct nand_chip *chip,
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const struct nand_operation *op,
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bool check_only)
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{
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struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
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struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
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struct ingenic_nand_cs *cs;
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unsigned int i;
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int ret = 0;
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if (check_only)
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return 0;
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cs = &nfc->cs[op->cs];
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jz4780_nemc_assert(nfc->dev, cs->bank, true);
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for (i = 0; i < op->ninstrs; i++) {
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ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
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if (ret)
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break;
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if (op->instrs[i].delay_ns)
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ndelay(op->instrs[i].delay_ns);
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}
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jz4780_nemc_assert(nfc->dev, cs->bank, false);
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return ret;
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}
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static const struct nand_controller_ops ingenic_nand_controller_ops = {
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.attach_chip = ingenic_nand_attach_chip,
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.exec_op = ingenic_nand_exec_op,
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};
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static int ingenic_nand_init_chip(struct platform_device *pdev,
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@ -339,8 +373,6 @@ static int ingenic_nand_init_chip(struct platform_device *pdev,
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ret = PTR_ERR(nand->busy_gpio);
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dev_err(dev, "failed to request busy GPIO: %d\n", ret);
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return ret;
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} else if (nand->busy_gpio) {
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nand->chip.legacy.dev_ready = ingenic_nand_dev_ready;
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}
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/*
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@ -371,12 +403,7 @@ static int ingenic_nand_init_chip(struct platform_device *pdev,
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return -ENOMEM;
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mtd->dev.parent = dev;
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chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset;
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chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset;
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chip->legacy.chip_delay = RB_DELAY_US;
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chip->options = NAND_NO_SUBPAGE_WRITE;
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chip->legacy.select_chip = ingenic_nand_select_chip;
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chip->legacy.cmd_ctrl = ingenic_nand_cmd_ctrl;
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chip->ecc.mode = NAND_ECC_HW;
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chip->controller = &nfc->controller;
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nand_set_flash_node(chip, np);
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