mmc: tmio: add new TMIO_MMC_HAVE_HIGH_REG flags
The accessibility checking method to the higher register was added by
69d1fe18e9
(mmc: tmio: only access registers above 0xff, if available)
But, it doesn't care 32bit register. It is impossible to calculate it
from the resource size, since there is 16/32 bit register IP (e.g. VERSION
is located on 0xe2 if 16bit register, but it is located on 0x1c4 if 32bit
register).
This patch adds new TMIO_MMC_HAVE_HIGH_REG flags, tmio_mmc driver has it,
and sh_mobile_sdhi doesn't have it today.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Родитель
3b159a6e95
Коммит
5d60e50054
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@ -91,6 +91,7 @@ static int tmio_mmc_probe(struct platform_device *pdev)
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/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
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/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
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pdata->bus_shift = resource_size(res_ctl) >> 10;
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pdata->bus_shift = resource_size(res_ctl) >> 10;
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pdata->flags |= TMIO_MMC_HAVE_HIGH_REG;
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ret = tmio_mmc_host_probe(&host, pdev, pdata);
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ret = tmio_mmc_host_probe(&host, pdev, pdata);
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if (ret)
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if (ret)
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@ -161,10 +161,8 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
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static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
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static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
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{
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{
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struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
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/* implicit BUG_ON(!res) */
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/* implicit BUG_ON(!res) */
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if (resource_size(res) > 0x100) {
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if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
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msleep(10);
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msleep(10);
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}
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}
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@ -176,14 +174,12 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
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static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
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static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
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{
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{
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struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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msleep(10);
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msleep(10);
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/* implicit BUG_ON(!res) */
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/* implicit BUG_ON(!res) */
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if (resource_size(res) > 0x100) {
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if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
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msleep(10);
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msleep(10);
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}
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}
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@ -191,16 +187,14 @@ static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
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static void tmio_mmc_reset(struct tmio_mmc_host *host)
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static void tmio_mmc_reset(struct tmio_mmc_host *host)
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{
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{
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struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
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/* FIXME - should we set stop clock reg here */
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/* FIXME - should we set stop clock reg here */
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sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
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sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
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/* implicit BUG_ON(!res) */
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/* implicit BUG_ON(!res) */
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if (resource_size(res) > 0x100)
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if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
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sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
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sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
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msleep(10);
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msleep(10);
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sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
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sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
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if (resource_size(res) > 0x100)
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if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
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sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
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sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
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msleep(10);
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msleep(10);
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}
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}
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@ -76,6 +76,13 @@
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*/
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*/
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#define TMIO_MMC_USE_GPIO_CD (1 << 5)
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#define TMIO_MMC_USE_GPIO_CD (1 << 5)
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/*
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* Some controllers doesn't have over 0x100 register.
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* it is used to checking accessibility of
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* CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
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*/
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#define TMIO_MMC_HAVE_HIGH_REG (1 << 6)
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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