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powerpc/64s/exception: Make EXCEPTION_PROLOG_0 a gas macro for consistency with others 

No generated code change.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Nicholas Piggin 2019-06-22 23:15:19 +10:00 коммит произвёл Michael Ellerman
Родитель c0c6cd156c
Коммит 5dba1d50ba
2 изменённых файлов: 25 добавлений и 24 удалений
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25
arch/powerpc/include/asm/exception-64s.h
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@ -237,7 +237,7 @@
*/ */
#define EXCEPTION_RELON_PROLOG(area, label, hsrr, kvm, vec) \ #define EXCEPTION_RELON_PROLOG(area, label, hsrr, kvm, vec) \
SET_SCRATCH0(r13); /* save r13 */ \ SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0(area); \ EXCEPTION_PROLOG_0 area ; \
EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \ EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \
EXCEPTION_PROLOG_2_VIRT label, hsrr EXCEPTION_PROLOG_2_VIRT label, hsrr
@ -301,13 +301,14 @@ BEGIN_FTR_SECTION_NESTED(943) \
std ra,offset(r13); \ std ra,offset(r13); \
END_FTR_SECTION_NESTED(ftr,ftr,943) END_FTR_SECTION_NESTED(ftr,ftr,943)
#define EXCEPTION_PROLOG_0(area) \ .macro EXCEPTION_PROLOG_0 area
GET_PACA(r13); \ GET_PACA(r13)
std r9,area+EX_R9(r13); /* save r9 */ \ std r9,\area\()+EX_R9(r13) /* save r9 */
OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
HMT_MEDIUM; \ HMT_MEDIUM
std r10,area+EX_R10(r13); /* save r10 - r12 */ \ std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
.endm
.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask .macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
@ -352,7 +353,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
#define EXCEPTION_PROLOG(area, label, hsrr, kvm, vec) \ #define EXCEPTION_PROLOG(area, label, hsrr, kvm, vec) \
SET_SCRATCH0(r13); /* save r13 */ \ SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0(area); \ EXCEPTION_PROLOG_0 area ; \
EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \ EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \
EXCEPTION_PROLOG_2_REAL label, hsrr, 1 EXCEPTION_PROLOG_2_REAL label, hsrr, 1
@ -421,7 +422,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
/* Do not enable RI */ /* Do not enable RI */
#define EXCEPTION_PROLOG_NORI(area, label, hsrr, kvm, vec) \ #define EXCEPTION_PROLOG_NORI(area, label, hsrr, kvm, vec) \
EXCEPTION_PROLOG_0(area); \ EXCEPTION_PROLOG_0 area ; \
EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \ EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, 0 ; \
EXCEPTION_PROLOG_2_REAL label, hsrr, 0 EXCEPTION_PROLOG_2_REAL label, hsrr, 0
@ -570,7 +571,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
/* Version of above for when we have to branch out-of-line */ /* Version of above for when we have to branch out-of-line */
#define __OOL_EXCEPTION(vec, label, hdlr) \ #define __OOL_EXCEPTION(vec, label, hdlr) \
SET_SCRATCH0(r13); \ SET_SCRATCH0(r13); \
EXCEPTION_PROLOG_0(PACA_EXGEN); \ EXCEPTION_PROLOG_0 PACA_EXGEN ; \
b hdlr b hdlr
#define STD_EXCEPTION_OOL(vec, label) \ #define STD_EXCEPTION_OOL(vec, label) \
@ -601,7 +602,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
#define __MASKABLE_EXCEPTION(vec, label, hsrr, kvm, bitmask) \ #define __MASKABLE_EXCEPTION(vec, label, hsrr, kvm, bitmask) \
SET_SCRATCH0(r13); /* save r13 */ \ SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0(PACA_EXGEN); \ EXCEPTION_PROLOG_0 PACA_EXGEN ; \
EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \ EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \
EXCEPTION_PROLOG_2_REAL label, hsrr, 1 EXCEPTION_PROLOG_2_REAL label, hsrr, 1
@ -621,7 +622,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
#define __MASKABLE_RELON_EXCEPTION(vec, label, hsrr, kvm, bitmask) \ #define __MASKABLE_RELON_EXCEPTION(vec, label, hsrr, kvm, bitmask) \
SET_SCRATCH0(r13); /* save r13 */ \ SET_SCRATCH0(r13); /* save r13 */ \
EXCEPTION_PROLOG_0(PACA_EXGEN); \ EXCEPTION_PROLOG_0 PACA_EXGEN ; \
EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \ EXCEPTION_PROLOG_1 hsrr, PACA_EXGEN, kvm, vec, bitmask ; \
EXCEPTION_PROLOG_2_VIRT label, hsrr EXCEPTION_PROLOG_2_VIRT label, hsrr

24
arch/powerpc/kernel/exceptions-64s.S
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@ -109,7 +109,7 @@ EXC_VIRT_NONE(0x4000, 0x100)
EXC_REAL_BEGIN(system_reset, 0x100, 0x100) EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
SET_SCRATCH0(r13) SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXNMI) EXCEPTION_PROLOG_0 PACA_EXNMI
/* This is EXCEPTION_PROLOG_1 with the idle feature section added */ /* This is EXCEPTION_PROLOG_1 with the idle feature section added */
OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR) OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR)
@ -266,7 +266,7 @@ EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
* vector * vector
*/ */
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXMC) EXCEPTION_PROLOG_0 PACA_EXMC
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
b machine_check_common_early b machine_check_common_early
FTR_SECTION_ELSE FTR_SECTION_ELSE
@ -355,7 +355,7 @@ TRAMP_REAL_BEGIN(machine_check_pSeries)
.globl machine_check_fwnmi .globl machine_check_fwnmi
machine_check_fwnmi: machine_check_fwnmi:
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXMC) EXCEPTION_PROLOG_0 PACA_EXMC
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
b machine_check_common_early b machine_check_common_early
END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
@ -568,7 +568,7 @@ ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
/* Deliver the machine check to host kernel in V mode. */ /* Deliver the machine check to host kernel in V mode. */
MACHINE_CHECK_HANDLER_WINDUP MACHINE_CHECK_HANDLER_WINDUP
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXMC) EXCEPTION_PROLOG_0 PACA_EXMC
b machine_check_pSeries_0 b machine_check_pSeries_0
EXC_COMMON_BEGIN(unrecover_mce) EXC_COMMON_BEGIN(unrecover_mce)
@ -593,7 +593,7 @@ EXC_COMMON_BEGIN(mce_return)
EXC_REAL_BEGIN(data_access, 0x300, 0x80) EXC_REAL_BEGIN(data_access, 0x300, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXGEN) EXCEPTION_PROLOG_0 PACA_EXGEN
b tramp_real_data_access b tramp_real_data_access
EXC_REAL_END(data_access, 0x300, 0x80) EXC_REAL_END(data_access, 0x300, 0x80)
@ -612,7 +612,7 @@ EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access, 0x4300, 0x80) EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXGEN) EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
mfspr r11,SPRN_DSISR mfspr r11,SPRN_DSISR
@ -647,7 +647,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXSLB) EXCEPTION_PROLOG_0 PACA_EXSLB
b tramp_real_data_access_slb b tramp_real_data_access_slb
EXC_REAL_END(data_access_slb, 0x380, 0x80) EXC_REAL_END(data_access_slb, 0x380, 0x80)
@ -659,7 +659,7 @@ EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXSLB) EXCEPTION_PROLOG_0 PACA_EXSLB
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
std r10,PACA_EXSLB+EX_DAR(r13) std r10,PACA_EXSLB+EX_DAR(r13)
@ -778,7 +778,7 @@ EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
EXC_REAL_BEGIN(alignment, 0x600, 0x100) EXC_REAL_BEGIN(alignment, 0x600, 0x100)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXGEN) EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
mfspr r11,SPRN_DSISR mfspr r11,SPRN_DSISR
@ -789,7 +789,7 @@ EXC_REAL_END(alignment, 0x600, 0x100)
EXC_VIRT_BEGIN(alignment, 0x4600, 0x100) EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
SET_SCRATCH0(r13) /* save r13 */ SET_SCRATCH0(r13) /* save r13 */
EXCEPTION_PROLOG_0(PACA_EXGEN) EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0
mfspr r10,SPRN_DAR mfspr r10,SPRN_DAR
mfspr r11,SPRN_DSISR mfspr r11,SPRN_DSISR
@ -1167,7 +1167,7 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
.globl hmi_exception_after_realmode .globl hmi_exception_after_realmode
hmi_exception_after_realmode: hmi_exception_after_realmode:
SET_SCRATCH0(r13) SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXGEN) EXCEPTION_PROLOG_0 PACA_EXGEN
b tramp_real_hmi_exception b tramp_real_hmi_exception
EXC_COMMON_BEGIN(hmi_exception_common) EXC_COMMON_BEGIN(hmi_exception_common)
@ -1320,7 +1320,7 @@ EXC_VIRT_NONE(0x5400, 0x100)
EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
mtspr SPRN_SPRG_HSCRATCH0,r13 mtspr SPRN_SPRG_HSCRATCH0,r13
EXCEPTION_PROLOG_0(PACA_EXGEN) EXCEPTION_PROLOG_0 PACA_EXGEN
EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0
#ifdef CONFIG_PPC_DENORMALISATION #ifdef CONFIG_PPC_DENORMALISATION