kvm/ppc/mpic: in-kernel MPIC emulation
Hook the MPIC code up to the KVM interfaces, add locking, etc. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: add stub function for kvmppc_mpic_set_epr, non-booke, 64bit] Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -0,0 +1,37 @@
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MPIC interrupt controller
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=========================
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Device types supported:
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KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
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KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
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Only one MPIC instance, of any type, may be instantiated. The created
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MPIC will act as the system interrupt controller, connecting to each
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vcpu's interrupt inputs.
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Groups:
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KVM_DEV_MPIC_GRP_MISC
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Attributes:
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KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
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Base address of the 256 KiB MPIC register space. Must be
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naturally aligned. A value of zero disables the mapping.
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Reset value is zero.
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KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
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Access an MPIC register, as if the access were made from the guest.
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"attr" is the byte offset into the MPIC register space. Accesses
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must be 4-byte aligned.
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MSIs may be signaled by using this attribute group to write
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to the relevant MSIIR.
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KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
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IRQ input line for each standard openpic source. 0 is inactive and 1
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is active, regardless of interrupt sense.
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For edge-triggered interrupts: Writing 1 is considered an activating
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edge, and writing 0 is ignored. Reading returns 1 if a previously
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signaled edge has not been acknowledged, and 0 otherwise.
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"attr" is the IRQ number. IRQ numbers for standard sources are the
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byte offset of the relevant IVPR from EIVPR0, divided by 32.
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@ -361,6 +361,11 @@ struct kvmppc_slb {
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#define KVMPPC_BOOKE_MAX_IAC 4
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#define KVMPPC_BOOKE_MAX_DAC 2
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/* KVMPPC_EPR_USER takes precedence over KVMPPC_EPR_KERNEL */
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#define KVMPPC_EPR_NONE 0 /* EPR not supported */
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#define KVMPPC_EPR_USER 1 /* exit to userspace to fill EPR */
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#define KVMPPC_EPR_KERNEL 2 /* in-kernel irqchip */
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struct kvmppc_booke_debug_reg {
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u32 dbcr0;
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u32 dbcr1;
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@ -526,7 +531,7 @@ struct kvm_vcpu_arch {
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u8 sane;
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u8 cpu_type;
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u8 hcall_needed;
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u8 epr_enabled;
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u8 epr_flags; /* KVMPPC_EPR_xxx */
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u8 epr_needed;
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u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
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@ -593,5 +598,6 @@ struct kvm_vcpu_arch {
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#define KVM_MMIO_REG_FQPR 0x0060
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#define __KVM_HAVE_ARCH_WQP
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#define __KVM_HAVE_CREATE_DEVICE
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#endif /* __POWERPC_KVM_HOST_H__ */
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@ -164,6 +164,8 @@ extern int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu);
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extern int kvm_vm_ioctl_get_htab_fd(struct kvm *kvm, struct kvm_get_htab_fd *);
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int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq);
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/*
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* Cuts out inst bits with ordering according to spec.
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* That means the leftmost bit is zero. All given bits are included.
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@ -245,6 +247,9 @@ int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *);
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void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid);
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struct openpic;
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void kvmppc_mpic_put(struct openpic *opp);
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#ifdef CONFIG_KVM_BOOK3S_64_HV
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static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr)
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{
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@ -270,6 +275,18 @@ static inline void kvmppc_set_epr(struct kvm_vcpu *vcpu, u32 epr)
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#endif
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}
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#ifdef CONFIG_KVM_MPIC
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void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu);
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#else
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static inline void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu)
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{
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}
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#endif /* CONFIG_KVM_MPIC */
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int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
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struct kvm_config_tlb *cfg);
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int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu *vcpu,
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@ -382,6 +382,14 @@ struct kvm_get_htab_header {
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__u16 n_invalid;
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};
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/* Device control API: PPC-specific devices */
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#define KVM_DEV_MPIC_GRP_MISC 1
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#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
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#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */
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#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */
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/* One-Reg API: PPC-specific registers */
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#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
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#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
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#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
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@ -151,6 +151,15 @@ config KVM_E500MC
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If unsure, say N.
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config KVM_MPIC
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bool "KVM in-kernel MPIC emulation"
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depends on KVM
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help
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Enable support for emulating MPIC devices inside the
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host kernel, rather than relying on userspace to emulate.
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Currently, support is limited to certain versions of
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Freescale's MPIC implementation.
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source drivers/vhost/Kconfig
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endif # VIRTUALIZATION
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@ -103,6 +103,8 @@ kvm-book3s_32-objs := \
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book3s_32_mmu.o
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kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
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kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
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kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
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obj-$(CONFIG_KVM_440) += kvm.o
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@ -346,7 +346,7 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
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keep_irq = true;
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}
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if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_enabled)
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if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
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update_epr = true;
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switch (priority) {
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@ -427,8 +427,10 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
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set_guest_esr(vcpu, vcpu->arch.queued_esr);
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if (update_dear == true)
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set_guest_dear(vcpu, vcpu->arch.queued_dear);
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if (update_epr == true)
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kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
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if (update_epr == true) {
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if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
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kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
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}
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new_msr &= msr_mask;
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#if defined(CONFIG_64BIT)
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@ -317,6 +317,7 @@ int kvm_dev_ioctl_check_extension(long ext)
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case KVM_CAP_ENABLE_CAP:
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case KVM_CAP_ONE_REG:
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case KVM_CAP_IOEVENTFD:
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case KVM_CAP_DEVICE_CTRL:
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r = 1;
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break;
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#ifndef CONFIG_KVM_BOOK3S_64_HV
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@ -762,7 +763,10 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
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break;
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case KVM_CAP_PPC_EPR:
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r = 0;
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vcpu->arch.epr_enabled = cap->args[0];
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if (cap->args[0])
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vcpu->arch.epr_flags |= KVMPPC_EPR_USER;
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else
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vcpu->arch.epr_flags &= ~KVMPPC_EPR_USER;
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break;
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#ifdef CONFIG_BOOKE
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case KVM_CAP_PPC_BOOKE_WATCHDOG:
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@ -908,6 +912,7 @@ static int kvm_vm_ioctl_get_pvinfo(struct kvm_ppc_pvinfo *pvinfo)
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long kvm_arch_vm_ioctl(struct file *filp,
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unsigned int ioctl, unsigned long arg)
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{
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struct kvm *kvm __maybe_unused = filp->private_data;
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void __user *argp = (void __user *)arg;
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long r;
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#ifdef CONFIG_PPC_BOOK3S_64
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case KVM_CREATE_SPAPR_TCE: {
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struct kvm_create_spapr_tce create_tce;
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struct kvm *kvm = filp->private_data;
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r = -EFAULT;
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if (copy_from_user(&create_tce, argp, sizeof(create_tce)))
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#ifdef CONFIG_KVM_BOOK3S_64_HV
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case KVM_ALLOCATE_RMA: {
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struct kvm *kvm = filp->private_data;
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struct kvm_allocate_rma rma;
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r = kvm_vm_ioctl_allocate_rma(kvm, &rma);
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}
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case KVM_PPC_ALLOCATE_HTAB: {
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struct kvm *kvm = filp->private_data;
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u32 htab_order;
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r = -EFAULT;
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}
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case KVM_PPC_GET_HTAB_FD: {
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struct kvm *kvm = filp->private_data;
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struct kvm_get_htab_fd ghf;
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r = -EFAULT;
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#ifdef CONFIG_PPC_BOOK3S_64
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case KVM_PPC_GET_SMMU_INFO: {
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struct kvm *kvm = filp->private_data;
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struct kvm_ppc_smmu_info info;
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memset(&info, 0, sizeof(info));
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void kvm_device_put(struct kvm_device *dev);
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struct kvm_device *kvm_device_from_filp(struct file *filp);
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extern struct kvm_device_ops kvm_mpic_ops;
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#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
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static inline void kvm_vcpu_set_in_spin_loop(struct kvm_vcpu *vcpu, bool val)
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__u64 addr; /* userspace address of attr data */
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};
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#define KVM_DEV_TYPE_FSL_MPIC_20 1
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#define KVM_DEV_TYPE_FSL_MPIC_42 2
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/*
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* ioctls for VM fds
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*/
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int ret;
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switch (cd->type) {
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#ifdef CONFIG_KVM_MPIC
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case KVM_DEV_TYPE_FSL_MPIC_20:
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case KVM_DEV_TYPE_FSL_MPIC_42:
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ops = &kvm_mpic_ops;
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break;
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#endif
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default:
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return -ENODEV;
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}
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