ASoC: rt5677: add GPIO IRQ support
This allows to enable Mic Jack detection feature Signed-off-by: Oder Chiou <oder_chiou@realtek.com> Modified-by: Anatol Pomozov <anatol.pomozov@gmail.com> Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Oder Chiou
Mark Brown
Родитель
ac884fc47b
Коммит
5e3363ad1b
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@ -33,6 +33,15 @@ Optional properties:
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1 - pull down
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2 - pull up
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- realtek,jd1-gpio
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Configures GPIO Mic Jack detection 1.
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Select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively.
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- realtek,jd2-gpio
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- realtek,jd3-gpio
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Configures GPIO Mic Jack detection 2 and 3.
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Select 0 ~ 3 as OFF, GPIO4, GPIO5 and GPIO6 respectively.
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Pins on the device (for linking into audio routes):
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* IN1P
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@ -63,4 +72,5 @@ rt5677 {
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<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
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realtek,in1-differential = "true";
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realtek,gpio-config = /bits/ 8 <0 0 0 0 0 2>; /* pull up GPIO6 */
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realtek,jd2-gpio = <3>; /* Enables Jack detection for GPIO6 */
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};
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@ -30,6 +30,13 @@ struct rt5677_platform_data {
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/* configures GPIO, 0 - floating, 1 - pulldown, 2 - pullup */
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u8 gpio_config[6];
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/* jd1 can select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively */
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unsigned int jd1_gpio;
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/* jd2 and jd3 can select 0 ~ 3 as
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OFF, GPIO4, GPIO5 and GPIO6 respectively */
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unsigned int jd2_gpio;
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unsigned int jd3_gpio;
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};
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#endif
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@ -3614,6 +3614,46 @@ static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
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}
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}
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static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
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struct regmap_irq_chip_data *data = rt5677->irq_data;
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int irq;
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if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
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if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
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(rt5677->pdata.jd1_gpio == 2 &&
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offset == RT5677_GPIO2) ||
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(rt5677->pdata.jd1_gpio == 3 &&
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offset == RT5677_GPIO3)) {
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irq = RT5677_IRQ_JD1;
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} else {
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return -ENXIO;
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}
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}
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if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
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if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
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(rt5677->pdata.jd2_gpio == 2 &&
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offset == RT5677_GPIO5) ||
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(rt5677->pdata.jd2_gpio == 3 &&
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offset == RT5677_GPIO6)) {
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irq = RT5677_IRQ_JD2;
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} else if ((rt5677->pdata.jd3_gpio == 1 &&
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offset == RT5677_GPIO4) ||
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(rt5677->pdata.jd3_gpio == 2 &&
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offset == RT5677_GPIO5) ||
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(rt5677->pdata.jd3_gpio == 3 &&
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offset == RT5677_GPIO6)) {
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irq = RT5677_IRQ_JD3;
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} else {
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return -ENXIO;
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}
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}
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return regmap_irq_get_virq(data, irq);
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}
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static struct gpio_chip rt5677_template_chip = {
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.label = "rt5677",
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.owner = THIS_MODULE,
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@ -3621,6 +3661,7 @@ static struct gpio_chip rt5677_template_chip = {
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.set = rt5677_gpio_set,
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.direction_input = rt5677_gpio_direction_in,
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.get = rt5677_gpio_get,
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.to_irq = rt5677_to_irq,
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.can_sleep = 1,
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};
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@ -3685,6 +3726,31 @@ static int rt5677_probe(struct snd_soc_codec *codec)
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for (i = 0; i < RT5677_GPIO_NUM; i++)
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rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
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if (rt5677->irq_data) {
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regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
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0x8000);
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regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
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0x0008);
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if (rt5677->pdata.jd1_gpio)
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regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
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RT5677_SEL_GPIO_JD1_MASK,
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rt5677->pdata.jd1_gpio <<
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RT5677_SEL_GPIO_JD1_SFT);
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if (rt5677->pdata.jd2_gpio)
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regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
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RT5677_SEL_GPIO_JD2_MASK,
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rt5677->pdata.jd2_gpio <<
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RT5677_SEL_GPIO_JD2_SFT);
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if (rt5677->pdata.jd3_gpio)
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regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
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RT5677_SEL_GPIO_JD3_MASK,
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rt5677->pdata.jd3_gpio <<
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RT5677_SEL_GPIO_JD3_SFT);
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}
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mutex_init(&rt5677->dsp_cmd_lock);
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return 0;
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@ -3915,9 +3981,74 @@ static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
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of_property_read_u8_array(np, "realtek,gpio-config",
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rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
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of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
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of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
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of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
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return 0;
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}
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static struct regmap_irq rt5677_irqs[] = {
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[RT5677_IRQ_JD1] = {
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.reg_offset = 0,
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.mask = RT5677_EN_IRQ_GPIO_JD1,
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},
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[RT5677_IRQ_JD2] = {
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.reg_offset = 0,
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.mask = RT5677_EN_IRQ_GPIO_JD2,
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},
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[RT5677_IRQ_JD3] = {
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.reg_offset = 0,
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.mask = RT5677_EN_IRQ_GPIO_JD3,
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},
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};
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static struct regmap_irq_chip rt5677_irq_chip = {
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.name = "rt5677",
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.irqs = rt5677_irqs,
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.num_irqs = ARRAY_SIZE(rt5677_irqs),
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.num_regs = 1,
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.status_base = RT5677_IRQ_CTRL1,
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.mask_base = RT5677_IRQ_CTRL1,
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.mask_invert = 1,
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};
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int rt5677_irq_init(struct i2c_client *i2c)
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{
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int ret;
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struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
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if (!rt5677->pdata.jd1_gpio &&
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!rt5677->pdata.jd2_gpio &&
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!rt5677->pdata.jd3_gpio)
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return 0;
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if (!i2c->irq) {
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dev_err(&i2c->dev, "No interrupt specified\n");
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return -EINVAL;
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}
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ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
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IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
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&rt5677_irq_chip, &rt5677->irq_data);
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if (ret != 0) {
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dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
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return ret;
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}
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return 0;
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}
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void rt5677_irq_exit(struct i2c_client *i2c)
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{
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struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
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if (rt5677->irq_data)
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regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
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}
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static int rt5677_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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@ -4015,6 +4146,7 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
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}
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rt5677_init_gpio(i2c);
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rt5677_irq_init(i2c);
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return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
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rt5677_dai, ARRAY_SIZE(rt5677_dai));
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@ -4022,6 +4154,8 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
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static int rt5677_i2c_remove(struct i2c_client *i2c)
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{
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rt5677_irq_exit(i2c);
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snd_soc_unregister_codec(&i2c->dev);
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rt5677_free_gpio(i2c);
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@ -1368,6 +1368,48 @@
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#define RT5677_SEL_SRC_IB01 (0x1 << 0)
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#define RT5677_SEL_SRC_IB01_SFT 0
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/* Jack Detect Control 1 (0xb5) */
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#define RT5677_SEL_GPIO_JD1_MASK (0x3 << 14)
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#define RT5677_SEL_GPIO_JD1_SFT 14
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#define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12)
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#define RT5677_SEL_GPIO_JD2_SFT 12
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#define RT5677_SEL_GPIO_JD3_MASK (0x3 << 10)
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#define RT5677_SEL_GPIO_JD3_SFT 10
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/* IRQ Control 1 (0xbd) */
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#define RT5677_STA_GPIO_JD1 (0x1 << 15)
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#define RT5677_STA_GPIO_JD1_SFT 15
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#define RT5677_EN_IRQ_GPIO_JD1 (0x1 << 14)
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#define RT5677_EN_IRQ_GPIO_JD1_SFT 14
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#define RT5677_EN_GPIO_JD1_STICKY (0x1 << 13)
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#define RT5677_EN_GPIO_JD1_STICKY_SFT 13
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#define RT5677_INV_GPIO_JD1 (0x1 << 12)
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#define RT5677_INV_GPIO_JD1_SFT 12
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#define RT5677_STA_GPIO_JD2 (0x1 << 11)
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#define RT5677_STA_GPIO_JD2_SFT 11
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#define RT5677_EN_IRQ_GPIO_JD2 (0x1 << 10)
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#define RT5677_EN_IRQ_GPIO_JD2_SFT 10
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#define RT5677_EN_GPIO_JD2_STICKY (0x1 << 9)
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#define RT5677_EN_GPIO_JD2_STICKY_SFT 9
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#define RT5677_INV_GPIO_JD2 (0x1 << 8)
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#define RT5677_INV_GPIO_JD2_SFT 8
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#define RT5677_STA_MICBIAS1_OVCD (0x1 << 7)
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#define RT5677_STA_MICBIAS1_OVCD_SFT 7
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#define RT5677_EN_IRQ_MICBIAS1_OVCD (0x1 << 6)
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#define RT5677_EN_IRQ_MICBIAS1_OVCD_SFT 6
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#define RT5677_EN_MICBIAS1_OVCD_STICKY (0x1 << 5)
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#define RT5677_EN_MICBIAS1_OVCD_STICKY_SFT 5
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#define RT5677_INV_MICBIAS1_OVCD (0x1 << 4)
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#define RT5677_INV_MICBIAS1_OVCD_SFT 4
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#define RT5677_STA_GPIO_JD3 (0x1 << 3)
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#define RT5677_STA_GPIO_JD3_SFT 3
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#define RT5677_EN_IRQ_GPIO_JD3 (0x1 << 2)
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#define RT5677_EN_IRQ_GPIO_JD3_SFT 2
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#define RT5677_EN_GPIO_JD3_STICKY (0x1 << 1)
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#define RT5677_EN_GPIO_JD3_STICKY_SFT 1
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#define RT5677_INV_GPIO_JD3 (0x1 << 0)
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#define RT5677_INV_GPIO_JD3_SFT 0
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/* GPIO status (0xbf) */
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#define RT5677_GPIO6_STATUS_MASK (0x1 << 5)
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#define RT5677_GPIO6_STATUS_SFT 5
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@ -1545,6 +1587,12 @@ enum {
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RT5677_GPIO_NUM,
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};
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enum {
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RT5677_IRQ_JD1,
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RT5677_IRQ_JD2,
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RT5677_IRQ_JD3,
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};
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struct rt5677_priv {
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struct snd_soc_codec *codec;
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struct rt5677_platform_data pdata;
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@ -1565,6 +1613,7 @@ struct rt5677_priv {
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struct gpio_chip gpio_chip;
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#endif
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bool dsp_vad_en;
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struct regmap_irq_chip_data *irq_data;
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};
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#endif /* __RT5677_H__ */
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