drm/amdgpu: move amdgpu_vce structure to vce header
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -60,6 +60,7 @@
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#include "amdgpu_dpm.h"
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#include "amdgpu_dpm.h"
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#include "amdgpu_acp.h"
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#include "amdgpu_acp.h"
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#include "amdgpu_uvd.h"
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#include "amdgpu_uvd.h"
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#include "amdgpu_vce.h"
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#include "gpu_scheduler.h"
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#include "gpu_scheduler.h"
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#include "amdgpu_virt.h"
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#include "amdgpu_virt.h"
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@ -1034,34 +1035,6 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
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void amdgpu_get_pcie_info(struct amdgpu_device *adev);
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void amdgpu_get_pcie_info(struct amdgpu_device *adev);
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/*
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* VCE
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*/
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#define AMDGPU_MAX_VCE_HANDLES 16
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#define AMDGPU_VCE_FIRMWARE_OFFSET 256
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#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
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#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
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struct amdgpu_vce {
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struct amdgpu_bo *vcpu_bo;
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uint64_t gpu_addr;
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unsigned fw_version;
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unsigned fb_version;
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atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
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struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
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uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
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struct delayed_work idle_work;
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struct mutex idle_mutex;
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const struct firmware *fw; /* VCE firmware */
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struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
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struct amdgpu_irq_src irq;
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unsigned harvest_config;
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struct amd_sched_entity entity;
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uint32_t srbm_soft_reset;
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unsigned num_rings;
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};
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/*
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/*
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* SDMA
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* SDMA
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*/
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*/
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@ -24,6 +24,31 @@
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#ifndef __AMDGPU_VCE_H__
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#ifndef __AMDGPU_VCE_H__
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#define __AMDGPU_VCE_H__
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#define __AMDGPU_VCE_H__
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#define AMDGPU_MAX_VCE_HANDLES 16
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#define AMDGPU_VCE_FIRMWARE_OFFSET 256
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#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
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#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
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struct amdgpu_vce {
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struct amdgpu_bo *vcpu_bo;
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uint64_t gpu_addr;
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unsigned fw_version;
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unsigned fb_version;
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atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
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struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
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uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
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struct delayed_work idle_work;
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struct mutex idle_mutex;
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const struct firmware *fw; /* VCE firmware */
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struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
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struct amdgpu_irq_src irq;
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unsigned harvest_config;
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struct amd_sched_entity entity;
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uint32_t srbm_soft_reset;
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unsigned num_rings;
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};
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int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
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int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
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int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
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int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
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int amdgpu_vce_suspend(struct amdgpu_device *adev);
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int amdgpu_vce_suspend(struct amdgpu_device *adev);
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