arm64: dts: mt8183: add mmc node
Add mmc DTS node to the mt8183 and mt8183-evb. Signed-off-by: Jjian Zhou <jjian.zhou-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> Link: https://lore.kernel.org/r/1554888341-5249-1-git-send-email-jjian.zhou@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
jjian zhou
Matthias Brugger
Родитель
e9cabfd046
Коммит
5e6cdf0051
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@ -73,6 +73,47 @@
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clock-frequency = <1000000>;
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};
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&mmc0 {
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status = "okay";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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bus-width = <8>;
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max-frequency = <200000000>;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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cap-mmc-hw-reset;
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no-sdio;
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no-sd;
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hs400-ds-delay = <0x12814>;
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vmmc-supply = <&mt6358_vemc_reg>;
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vqmmc-supply = <&mt6358_vio18_reg>;
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assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
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assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
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non-removable;
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};
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&mmc1 {
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status = "okay";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc1_pins_default>;
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pinctrl-1 = <&mmc1_pins_uhs>;
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bus-width = <4>;
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max-frequency = <200000000>;
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cap-sd-highspeed;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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cap-sdio-irq;
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no-mmc;
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no-sd;
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vmmc-supply = <&mt6358_vmch_reg>;
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vqmmc-supply = <&mt6358_vmc_reg>;
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keep-power-in-suspend;
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enable-sdio-wakeup;
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non-removable;
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};
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&pio {
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i2c_pins_0: i2c0{
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pins_i2c{
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@ -138,6 +179,111 @@
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};
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};
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mmc0_pins_default: mmc0default {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
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<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
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<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
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<PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
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<PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
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<PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
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<PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
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<PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
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<PINMUX_GPIO122__FUNC_MSDC0_CMD>;
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input-enable;
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bias-pull-up;
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};
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pins_clk {
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pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
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bias-pull-down;
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};
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pins_rst {
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pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
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bias-pull-up;
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};
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};
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mmc0_pins_uhs: mmc0@0{
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
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<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
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<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
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<PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
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<PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
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<PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
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<PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
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<PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
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<PINMUX_GPIO122__FUNC_MSDC0_CMD>;
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input-enable;
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drive-strength = <MTK_DRIVE_10mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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pins_clk {
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pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
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drive-strength = <MTK_DRIVE_10mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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pins_ds {
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pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
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drive-strength = <MTK_DRIVE_10mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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pins_rst {
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pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
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drive-strength = <MTK_DRIVE_10mA>;
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bias-pull-up;
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};
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};
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mmc1_pins_default: mmc1default {
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
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<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
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<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
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<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
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<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
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input-enable;
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bias-pull-up;
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};
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pins_clk {
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pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
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input-enable;
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bias-pull-down;
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};
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pins_pmu {
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pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
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<PINMUX_GPIO166__FUNC_GPIO166>;
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output-high;
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};
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};
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mmc1_pins_uhs: mmc1@0{
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pins_cmd_dat {
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pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
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<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
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<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
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<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
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<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
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drive-strength = <MTK_DRIVE_6mA>;
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input-enable;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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pins_clk {
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pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
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drive-strength = <MTK_DRIVE_6mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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input-enable;
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};
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};
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spi_pins_1: spi1{
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pins_spi{
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pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
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@ -648,6 +648,30 @@
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#clock-cells = <1>;
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8183-mmc";
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reg = <0 0x11230000 0 0x1000>,
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<0 0x11f50000 0 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
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<&infracfg CLK_INFRA_MSDC0>,
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<&infracfg CLK_INFRA_MSDC0_SCK>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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mmc1: mmc@11240000 {
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compatible = "mediatek,mt8183-mmc";
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reg = <0 0x11240000 0 0x1000>,
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<0 0x11e10000 0 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
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<&infracfg CLK_INFRA_MSDC1>,
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<&infracfg CLK_INFRA_MSDC1_SCK>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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efuse: efuse@11f10000 {
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compatible = "mediatek,mt8183-efuse",
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"mediatek,efuse";
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