Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/kms: add new radeon_info ioctl query for clock crystal freq drm/i915: Prevent uninitialised reads during error state capture drm/i915: Use consistent mappings for OpRegion between ACPI and i915 drm/i915: Handle the no-interrupts case for UMS by polling drm/i915: Disable high-precision vblank timestamping for UMS drm/i915: Increase the amount of defense before computing vblank timestamps drm/i915,agp/intel: Do not clear stolen entries drm/radeon/kms: simplify atom adjust pll setup drm/radeon/kms: match r6xx/r7xx/evergreen asic_reset with previous asics drm/radeon/kms: make the mac rv630 quirk generic drm/radeon/kms: fix a spelling error in an error message drm/radeon/kms: Initialize pageflip spinlocks. drm/i915: Recognise non-VGA display devices drm/i915: Fix use of invalid array size for ring->sync_seqno drm/i915/ringbuffer: Fix use of stale HEAD position whilst polling for space drm/i915: Don't kick-off hangcheck after a DRI interrupt drm/i915: Add dependency on CONFIG_TMPFS drm/i915: Initialise ring vfuncs for old DRI paths drm/i915: make the blitter report buffer modifications to the FBC unit drm/i915: set more FBC chicken bits
This commit is contained in:
Linus Torvalds
Коммит
5e82ea9982
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@ -68,6 +68,7 @@ static struct _intel_private {
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phys_addr_t gma_bus_addr;
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u32 PGETBL_save;
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u32 __iomem *gtt; /* I915G */
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bool clear_fake_agp; /* on first access via agp, fill with scratch */
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int num_dcache_entries;
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union {
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void __iomem *i9xx_flush_page;
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@ -869,21 +870,12 @@ static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
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static int intel_fake_agp_configure(void)
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{
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int i;
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if (!intel_enable_gtt())
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return -EIO;
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intel_private.clear_fake_agp = true;
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agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
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for (i = 0; i < intel_private.base.gtt_total_entries; i++) {
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intel_private.driver->write_entry(intel_private.scratch_page_dma,
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i, 0);
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}
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readl(intel_private.gtt+i-1); /* PCI Posting. */
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global_cache_flush();
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return 0;
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}
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@ -945,6 +937,13 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
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{
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int ret = -EINVAL;
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if (intel_private.clear_fake_agp) {
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int start = intel_private.base.stolen_size / PAGE_SIZE;
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int end = intel_private.base.gtt_mappable_entries;
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intel_gtt_clear_range(start, end - start);
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intel_private.clear_fake_agp = false;
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}
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if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
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return i810_insert_dcache_entries(mem, pg_start, type);
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@ -100,7 +100,10 @@ config DRM_I830
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config DRM_I915
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tristate "i915 driver"
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depends on AGP_INTEL
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# we need shmfs for the swappable backing store, and in particular
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# the shmem_readpage() which depends upon tmpfs
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select SHMEM
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select TMPFS
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select DRM_KMS_HELPER
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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@ -152,7 +152,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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struct intel_ring_buffer *ring = LP_RING(dev_priv);
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int ret;
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master_priv->sarea = drm_getsarea(dev);
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if (master_priv->sarea) {
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@ -163,33 +163,22 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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}
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if (init->ring_size != 0) {
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if (ring->obj != NULL) {
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if (LP_RING(dev_priv)->obj != NULL) {
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i915_dma_cleanup(dev);
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DRM_ERROR("Client tried to initialize ringbuffer in "
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"GEM mode\n");
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return -EINVAL;
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}
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ring->size = init->ring_size;
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ring->map.offset = init->ring_start;
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ring->map.size = init->ring_size;
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ring->map.type = 0;
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ring->map.flags = 0;
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ring->map.mtrr = 0;
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drm_core_ioremap_wc(&ring->map, dev);
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if (ring->map.handle == NULL) {
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ret = intel_render_ring_init_dri(dev,
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init->ring_start,
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init->ring_size);
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if (ret) {
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i915_dma_cleanup(dev);
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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return -ENOMEM;
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return ret;
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}
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}
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ring->virtual_start = ring->map.handle;
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dev_priv->cpp = init->cpp;
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dev_priv->back_offset = init->back_offset;
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dev_priv->front_offset = init->front_offset;
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@ -1226,9 +1215,15 @@ static int i915_load_modeset_init(struct drm_device *dev)
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if (ret)
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DRM_INFO("failed to find VBIOS tables\n");
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/* if we have > 1 VGA cards, then disable the radeon VGA resources */
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/* If we have > 1 VGA cards, then we need to arbitrate access
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* to the common VGA resources.
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*
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* If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
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* then we do not take part in VGA arbitration and the
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* vga_client_register() fails with -ENODEV.
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*/
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ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
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if (ret)
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if (ret && ret != -ENODEV)
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goto cleanup_ringbuffer;
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intel_register_dsm_handler();
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@ -60,7 +60,7 @@ extern int intel_agp_enabled;
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#define INTEL_VGA_DEVICE(id, info) { \
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.class = PCI_CLASS_DISPLAY_VGA << 8, \
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.class_mask = 0xffff00, \
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.class_mask = 0xff0000, \
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.vendor = 0x8086, \
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.device = id, \
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.subvendor = PCI_ANY_ID, \
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@ -752,6 +752,9 @@ static int __init i915_init(void)
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driver.driver_features &= ~DRIVER_MODESET;
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#endif
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if (!(driver.driver_features & DRIVER_MODESET))
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driver.get_vblank_timestamp = NULL;
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return drm_init(&driver);
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}
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@ -543,8 +543,11 @@ typedef struct drm_i915_private {
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/** List of all objects in gtt_space. Used to restore gtt
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* mappings on resume */
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struct list_head gtt_list;
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/** End of mappable part of GTT */
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/** Usable portion of the GTT for GEM */
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unsigned long gtt_start;
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unsigned long gtt_mappable_end;
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unsigned long gtt_end;
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struct io_mapping *gtt_mapping;
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int gtt_mtrr;
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@ -140,12 +140,16 @@ void i915_gem_do_init(struct drm_device *dev,
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_mm_init(&dev_priv->mm.gtt_space, start,
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end - start);
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drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
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dev_priv->mm.gtt_start = start;
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dev_priv->mm.gtt_mappable_end = mappable_end;
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dev_priv->mm.gtt_end = end;
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dev_priv->mm.gtt_total = end - start;
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dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
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dev_priv->mm.gtt_mappable_end = mappable_end;
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/* Take over this portion of the GTT */
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intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
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}
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int
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@ -1857,7 +1861,7 @@ i915_gem_retire_requests_ring(struct drm_device *dev,
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seqno = ring->get_seqno(ring);
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for (i = 0; i < I915_NUM_RINGS; i++)
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for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
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if (seqno >= ring->sync_seqno[i])
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ring->sync_seqno[i] = 0;
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@ -1175,7 +1175,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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goto err;
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seqno = i915_gem_next_request_seqno(dev, ring);
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for (i = 0; i < I915_NUM_RINGS-1; i++) {
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for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
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if (seqno < ring->sync_seqno[i]) {
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/* The GPU can not handle its semaphore value wrapping,
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* so every billion or so execbuffers, we need to stall
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@ -34,6 +34,10 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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/* First fill our portion of the GTT with scratch pages */
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intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
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(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
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list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
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i915_gem_clflush_object(obj);
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@ -274,24 +274,35 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
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return ret;
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}
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int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
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int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
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int *max_error,
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struct timeval *vblank_time,
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unsigned flags)
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{
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struct drm_crtc *drmcrtc;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc;
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if (crtc < 0 || crtc >= dev->num_crtcs) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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if (pipe < 0 || pipe >= dev_priv->num_pipe) {
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DRM_ERROR("Invalid crtc %d\n", pipe);
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return -EINVAL;
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}
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/* Get drm_crtc to timestamp: */
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drmcrtc = intel_get_crtc_for_pipe(dev, crtc);
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crtc = intel_get_crtc_for_pipe(dev, pipe);
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if (crtc == NULL) {
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DRM_ERROR("Invalid crtc %d\n", pipe);
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return -EINVAL;
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}
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if (!crtc->enabled) {
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DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
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return -EBUSY;
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}
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/* Helper routine in DRM core does all the work: */
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return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
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vblank_time, flags, drmcrtc);
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return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
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vblank_time, flags,
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crtc);
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}
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/*
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@ -348,8 +359,12 @@ static void notify_ring(struct drm_device *dev,
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struct intel_ring_buffer *ring)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 seqno = ring->get_seqno(ring);
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u32 seqno;
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if (ring->obj == NULL)
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return;
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seqno = ring->get_seqno(ring);
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trace_i915_gem_request_complete(dev, seqno);
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ring->irq_seqno = seqno;
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@ -831,6 +846,8 @@ static void i915_capture_error_state(struct drm_device *dev)
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i++;
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error->pinned_bo_count = i - error->active_bo_count;
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error->active_bo = NULL;
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error->pinned_bo = NULL;
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if (i) {
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||||
error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
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GFP_ATOMIC);
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|
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@ -1278,12 +1295,12 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
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|||
if (master_priv->sarea_priv)
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||||
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
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||||
|
||||
ret = -ENODEV;
|
||||
if (ring->irq_get(ring)) {
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||||
DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
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||||
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
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ring->irq_put(ring);
|
||||
}
|
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} else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
|
||||
ret = -EBUSY;
|
||||
|
||||
if (ret == -EBUSY) {
|
||||
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
|
||||
|
|
|
|||
|
|
@ -513,6 +513,10 @@
|
|||
#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
|
||||
#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
|
||||
|
||||
#define GEN6_BLITTER_ECOSKPD 0x221d0
|
||||
#define GEN6_BLITTER_LOCK_SHIFT 16
|
||||
#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
|
||||
|
||||
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
|
||||
#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
|
||||
#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
|
||||
|
|
@ -2626,6 +2630,8 @@
|
|||
#define DISPLAY_PORT_PLL_BIOS_2 0x46014
|
||||
|
||||
#define PCH_DSPCLK_GATE_D 0x42020
|
||||
# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
|
||||
# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
|
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# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
|
||||
# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
|
||||
|
||||
|
|
|
|||
|
|
@ -1213,6 +1213,26 @@ static bool g4x_fbc_enabled(struct drm_device *dev)
|
|||
return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
|
||||
}
|
||||
|
||||
static void sandybridge_blit_fbc_update(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
u32 blt_ecoskpd;
|
||||
|
||||
/* Make sure blitter notifies FBC of writes */
|
||||
__gen6_force_wake_get(dev_priv);
|
||||
blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
|
||||
blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
|
||||
GEN6_BLITTER_LOCK_SHIFT;
|
||||
I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
|
||||
blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
|
||||
I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
|
||||
blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
|
||||
GEN6_BLITTER_LOCK_SHIFT);
|
||||
I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
|
||||
POSTING_READ(GEN6_BLITTER_ECOSKPD);
|
||||
__gen6_force_wake_put(dev_priv);
|
||||
}
|
||||
|
||||
static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
|
|
@ -1266,6 +1286,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
|
|||
I915_WRITE(SNB_DPFC_CTL_SA,
|
||||
SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
|
||||
I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
|
||||
sandybridge_blit_fbc_update(dev);
|
||||
}
|
||||
|
||||
DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
|
||||
|
|
@ -6286,7 +6307,9 @@ void intel_enable_clock_gating(struct drm_device *dev)
|
|||
|
||||
if (IS_GEN5(dev)) {
|
||||
/* Required for FBC */
|
||||
dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
|
||||
dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
|
||||
DPFCRUNIT_CLOCK_GATE_DISABLE |
|
||||
DPFDUNIT_CLOCK_GATE_DISABLE;
|
||||
/* Required for CxSR */
|
||||
dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/acpi_io.h>
|
||||
#include <acpi/video.h>
|
||||
|
||||
#include "drmP.h"
|
||||
|
|
@ -476,7 +477,7 @@ int intel_opregion_setup(struct drm_device *dev)
|
|||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
base = ioremap(asls, OPREGION_SIZE);
|
||||
base = acpi_os_ioremap(asls, OPREGION_SIZE);
|
||||
if (!base)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,14 @@
|
|||
#include "i915_trace.h"
|
||||
#include "intel_drv.h"
|
||||
|
||||
static inline int ring_space(struct intel_ring_buffer *ring)
|
||||
{
|
||||
int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
|
||||
if (space < 0)
|
||||
space += ring->size;
|
||||
return space;
|
||||
}
|
||||
|
||||
static u32 i915_gem_get_seqno(struct drm_device *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
|
|
@ -204,11 +212,9 @@ static int init_ring_common(struct intel_ring_buffer *ring)
|
|||
if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
|
||||
i915_kernel_lost_context(ring->dev);
|
||||
else {
|
||||
ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
|
||||
ring->head = I915_READ_HEAD(ring);
|
||||
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
|
||||
ring->space = ring->head - (ring->tail + 8);
|
||||
if (ring->space < 0)
|
||||
ring->space += ring->size;
|
||||
ring->space = ring_space(ring);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -921,32 +927,34 @@ static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
|
|||
}
|
||||
|
||||
ring->tail = 0;
|
||||
ring->space = ring->head - 8;
|
||||
ring->space = ring_space(ring);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
|
||||
{
|
||||
int reread = 0;
|
||||
struct drm_device *dev = ring->dev;
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
unsigned long end;
|
||||
u32 head;
|
||||
|
||||
trace_i915_ring_wait_begin (dev);
|
||||
end = jiffies + 3 * HZ;
|
||||
do {
|
||||
/* If the reported head position has wrapped or hasn't advanced,
|
||||
* fallback to the slow and accurate path.
|
||||
*/
|
||||
head = intel_read_status_page(ring, 4);
|
||||
if (reread)
|
||||
head = I915_READ_HEAD(ring);
|
||||
ring->head = head & HEAD_ADDR;
|
||||
ring->space = ring->head - (ring->tail + 8);
|
||||
if (ring->space < 0)
|
||||
ring->space += ring->size;
|
||||
if (head > ring->head) {
|
||||
ring->head = head;
|
||||
ring->space = ring_space(ring);
|
||||
if (ring->space >= n)
|
||||
return 0;
|
||||
}
|
||||
|
||||
trace_i915_ring_wait_begin (dev);
|
||||
end = jiffies + 3 * HZ;
|
||||
do {
|
||||
ring->head = I915_READ_HEAD(ring);
|
||||
ring->space = ring_space(ring);
|
||||
if (ring->space >= n) {
|
||||
trace_i915_ring_wait_end(dev);
|
||||
return 0;
|
||||
|
|
@ -961,7 +969,6 @@ int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
|
|||
msleep(1);
|
||||
if (atomic_read(&dev_priv->mm.wedged))
|
||||
return -EAGAIN;
|
||||
reread = 1;
|
||||
} while (!time_after(jiffies, end));
|
||||
trace_i915_ring_wait_end (dev);
|
||||
return -EBUSY;
|
||||
|
|
@ -1292,6 +1299,48 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
|
|||
return intel_init_ring_buffer(dev, ring);
|
||||
}
|
||||
|
||||
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
|
||||
|
||||
*ring = render_ring;
|
||||
if (INTEL_INFO(dev)->gen >= 6) {
|
||||
ring->add_request = gen6_add_request;
|
||||
ring->irq_get = gen6_render_ring_get_irq;
|
||||
ring->irq_put = gen6_render_ring_put_irq;
|
||||
} else if (IS_GEN5(dev)) {
|
||||
ring->add_request = pc_render_add_request;
|
||||
ring->get_seqno = pc_render_get_seqno;
|
||||
}
|
||||
|
||||
ring->dev = dev;
|
||||
INIT_LIST_HEAD(&ring->active_list);
|
||||
INIT_LIST_HEAD(&ring->request_list);
|
||||
INIT_LIST_HEAD(&ring->gpu_write_list);
|
||||
|
||||
ring->size = size;
|
||||
ring->effective_size = ring->size;
|
||||
if (IS_I830(ring->dev))
|
||||
ring->effective_size -= 128;
|
||||
|
||||
ring->map.offset = start;
|
||||
ring->map.size = size;
|
||||
ring->map.type = 0;
|
||||
ring->map.flags = 0;
|
||||
ring->map.mtrr = 0;
|
||||
|
||||
drm_core_ioremap_wc(&ring->map, dev);
|
||||
if (ring->map.handle == NULL) {
|
||||
DRM_ERROR("can not ioremap virtual address for"
|
||||
" ring buffer\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ring->virtual_start = (void __force __iomem *)ring->map.handle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int intel_init_bsd_ring_buffer(struct drm_device *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
|
|
|
|||
|
|
@ -166,4 +166,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev);
|
|||
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
|
||||
void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
|
||||
|
||||
/* DRI warts */
|
||||
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
|
||||
|
||||
#endif /* _INTEL_RINGBUFFER_H_ */
|
||||
|
|
|
|||
|
|
@ -606,14 +606,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
|
|||
args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
|
||||
args.v1.ucTransmitterID = radeon_encoder->encoder_id;
|
||||
args.v1.ucEncodeMode = encoder_mode;
|
||||
if (encoder_mode == ATOM_ENCODER_MODE_DP) {
|
||||
if (ss_enabled)
|
||||
args.v1.ucConfig |=
|
||||
ADJUST_DISPLAY_CONFIG_SS_ENABLE;
|
||||
} else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
|
||||
args.v1.ucConfig |=
|
||||
ADJUST_DISPLAY_CONFIG_SS_ENABLE;
|
||||
}
|
||||
|
||||
atom_execute_table(rdev->mode_info.atom_context,
|
||||
index, (uint32_t *)&args);
|
||||
|
|
@ -624,12 +619,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
|
|||
args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
|
||||
args.v3.sInput.ucEncodeMode = encoder_mode;
|
||||
args.v3.sInput.ucDispPllConfig = 0;
|
||||
if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
|
||||
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
||||
if (encoder_mode == ATOM_ENCODER_MODE_DP) {
|
||||
if (ss_enabled)
|
||||
args.v3.sInput.ucDispPllConfig |=
|
||||
DISPPLL_CONFIG_SS_ENABLE;
|
||||
if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
|
||||
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
||||
if (encoder_mode == ATOM_ENCODER_MODE_DP) {
|
||||
args.v3.sInput.ucDispPllConfig |=
|
||||
DISPPLL_CONFIG_COHERENT_MODE;
|
||||
/* 16200 or 27000 */
|
||||
|
|
@ -649,18 +644,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
|
|||
}
|
||||
} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
|
||||
if (encoder_mode == ATOM_ENCODER_MODE_DP) {
|
||||
if (ss_enabled)
|
||||
args.v3.sInput.ucDispPllConfig |=
|
||||
DISPPLL_CONFIG_SS_ENABLE;
|
||||
args.v3.sInput.ucDispPllConfig |=
|
||||
DISPPLL_CONFIG_COHERENT_MODE;
|
||||
/* 16200 or 27000 */
|
||||
args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
|
||||
} else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
|
||||
if (ss_enabled)
|
||||
args.v3.sInput.ucDispPllConfig |=
|
||||
DISPPLL_CONFIG_SS_ENABLE;
|
||||
} else {
|
||||
} else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
|
||||
if (mode->clock > 165000)
|
||||
args.v3.sInput.ucDispPllConfig |=
|
||||
DISPPLL_CONFIG_DUAL_LINK;
|
||||
|
|
|
|||
|
|
@ -2201,6 +2201,9 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
|
|||
struct evergreen_mc_save save;
|
||||
u32 grbm_reset = 0;
|
||||
|
||||
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
|
||||
return 0;
|
||||
|
||||
dev_info(rdev->dev, "GPU softreset \n");
|
||||
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
|
||||
RREG32(GRBM_STATUS));
|
||||
|
|
|
|||
|
|
@ -3522,7 +3522,7 @@ int r100_ring_test(struct radeon_device *rdev)
|
|||
if (i < rdev->usec_timeout) {
|
||||
DRM_INFO("ring test succeeded in %d usecs\n", i);
|
||||
} else {
|
||||
DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
|
||||
DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
|
||||
scratch, tmp);
|
||||
r = -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1287,6 +1287,9 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
|
|||
S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
|
||||
u32 tmp;
|
||||
|
||||
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
|
||||
return 0;
|
||||
|
||||
dev_info(rdev->dev, "GPU softreset \n");
|
||||
dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
|
||||
RREG32(R_008010_GRBM_STATUS));
|
||||
|
|
|
|||
|
|
@ -387,16 +387,12 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
|
|||
*line_mux = 0x90;
|
||||
}
|
||||
|
||||
/* mac rv630 */
|
||||
if ((dev->pdev->device == 0x9588) &&
|
||||
(dev->pdev->subsystem_vendor == 0x106b) &&
|
||||
(dev->pdev->subsystem_device == 0x00a6)) {
|
||||
/* mac rv630, rv730, others */
|
||||
if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
|
||||
(*connector_type == DRM_MODE_CONNECTOR_DVII)) {
|
||||
*connector_type = DRM_MODE_CONNECTOR_9PinDIN;
|
||||
*line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
|
||||
}
|
||||
}
|
||||
|
||||
/* ASUS HD 3600 XT board lists the DVI port as HDMI */
|
||||
if ((dev->pdev->device == 0x9598) &&
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@
|
|||
* - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
|
||||
* - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
|
||||
* 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
|
||||
* 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK
|
||||
* 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
|
||||
*/
|
||||
#define KMS_DRIVER_MAJOR 2
|
||||
#define KMS_DRIVER_MINOR 8
|
||||
|
|
|
|||
|
|
@ -110,11 +110,14 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
|
|||
|
||||
int radeon_irq_kms_init(struct radeon_device *rdev)
|
||||
{
|
||||
int i;
|
||||
int r = 0;
|
||||
|
||||
INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
|
||||
|
||||
spin_lock_init(&rdev->irq.sw_lock);
|
||||
for (i = 0; i < rdev->num_crtc; i++)
|
||||
spin_lock_init(&rdev->irq.pflip_lock[i]);
|
||||
r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
|
||||
if (r) {
|
||||
return r;
|
||||
|
|
|
|||
|
|
@ -201,6 +201,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
|||
}
|
||||
radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
|
||||
break;
|
||||
case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
|
||||
/* return clock value in KHz */
|
||||
value = rdev->clock.spll.reference_freq * 10;
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -636,7 +636,7 @@ int vga_client_register(struct pci_dev *pdev, void *cookie,
|
|||
void (*irq_set_state)(void *cookie, bool state),
|
||||
unsigned int (*set_vga_decode)(void *cookie, bool decode))
|
||||
{
|
||||
int ret = -1;
|
||||
int ret = -ENODEV;
|
||||
struct vga_device *vgadev;
|
||||
unsigned long flags;
|
||||
|
||||
|
|
|
|||
|
|
@ -907,6 +907,7 @@ struct drm_radeon_cs {
|
|||
#define RADEON_INFO_TILING_CONFIG 0x06
|
||||
#define RADEON_INFO_WANT_HYPERZ 0x07
|
||||
#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */
|
||||
#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
|
||||
|
||||
struct drm_radeon_info {
|
||||
uint32_t request;
|
||||
|
|
|
|||
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