clk: sifive: Move all stuff into SoCs header files from C files
Improve PRCI driver to reduce the complexity, we remove the SoCs C files
by putting all stuff in each SoCs header files, and include these
SoCs-specific header files in core of PRCI. It can also avoid the W=1
kernel build warnings about variable defined but not used
[-Wunused-const-variable=], like commit 487dc7bb6a ("clk: sifive:
fu540-prci: Declare static const variable 'prci_clk_fu540' where it's
used") does.
Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/a3c7ec5c46c1d8be455d1c347db4855bb56cec53.1646388139.git.zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Zong Li
Stephen Boyd
Родитель
24a4a29f75
Коммит
5e916932df
|
|
@ -1,2 +1,2 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0-only
|
# SPDX-License-Identifier: GPL-2.0-only
|
||||||
obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o
|
obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o
|
||||||
|
|
|
||||||
|
|
@ -1,88 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2018-2022 SiFive, Inc.
|
|
||||||
* Copyright (C) 2018-2019 Wesley Terpstra
|
|
||||||
* Copyright (C) 2018-2019 Paul Walmsley
|
|
||||||
* Copyright (C) 2020-2022 Zong Li
|
|
||||||
*
|
|
||||||
* The FU540 PRCI implements clock and reset control for the SiFive
|
|
||||||
* FU540-C000 chip. This driver assumes that it has sole control
|
|
||||||
* over all PRCI resources.
|
|
||||||
*
|
|
||||||
* This driver is based on the PRCI driver written by Wesley Terpstra:
|
|
||||||
* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
|
|
||||||
*
|
|
||||||
* References:
|
|
||||||
* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/module.h>
|
|
||||||
|
|
||||||
#include <dt-bindings/clock/sifive-fu540-prci.h>
|
|
||||||
|
|
||||||
#include "sifive-prci.h"
|
|
||||||
|
|
||||||
/* PRCI integration data for each WRPLL instance */
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
|
|
||||||
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
|
||||||
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
|
|
||||||
.disable_bypass = sifive_prci_coreclksel_use_corepll,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
|
|
||||||
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
|
|
||||||
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Linux clock framework integration */
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
|
|
||||||
.set_rate = sifive_prci_wrpll_set_rate,
|
|
||||||
.round_rate = sifive_prci_wrpll_round_rate,
|
|
||||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
|
||||||
.enable = sifive_prci_clock_enable,
|
|
||||||
.disable = sifive_prci_clock_disable,
|
|
||||||
.is_enabled = sifive_clk_is_enabled,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
|
|
||||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
|
|
||||||
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* List of clock controls provided by the PRCI */
|
|
||||||
struct __prci_clock __prci_init_clocks_fu540[] = {
|
|
||||||
[FU540_PRCI_CLK_COREPLL] = {
|
|
||||||
.name = "corepll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
|
||||||
.pwd = &sifive_fu540_prci_corepll_data,
|
|
||||||
},
|
|
||||||
[FU540_PRCI_CLK_DDRPLL] = {
|
|
||||||
.name = "ddrpll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
|
|
||||||
.pwd = &sifive_fu540_prci_ddrpll_data,
|
|
||||||
},
|
|
||||||
[FU540_PRCI_CLK_GEMGXLPLL] = {
|
|
||||||
.name = "gemgxlpll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
|
||||||
.pwd = &sifive_fu540_prci_gemgxlpll_data,
|
|
||||||
},
|
|
||||||
[FU540_PRCI_CLK_TLCLK] = {
|
|
||||||
.name = "tlclk",
|
|
||||||
.parent_name = "corepll",
|
|
||||||
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
@ -1,16 +1,99 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2020 SiFive, Inc.
|
* Copyright (C) 2018-2021 SiFive, Inc.
|
||||||
* Zong Li
|
* Copyright (C) 2018-2019 Wesley Terpstra
|
||||||
|
* Copyright (C) 2018-2019 Paul Walmsley
|
||||||
|
* Copyright (C) 2020-2021 Zong Li
|
||||||
|
*
|
||||||
|
* The FU540 PRCI implements clock and reset control for the SiFive
|
||||||
|
* FU540-C000 chip. This driver assumes that it has sole control
|
||||||
|
* over all PRCI resources.
|
||||||
|
*
|
||||||
|
* This driver is based on the PRCI driver written by Wesley Terpstra:
|
||||||
|
* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
|
||||||
|
*
|
||||||
|
* References:
|
||||||
|
* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __SIFIVE_CLK_FU540_PRCI_H
|
#ifndef __SIFIVE_CLK_FU540_PRCI_H
|
||||||
#define __SIFIVE_CLK_FU540_PRCI_H
|
#define __SIFIVE_CLK_FU540_PRCI_H
|
||||||
|
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
|
||||||
|
#include <dt-bindings/clock/sifive-fu540-prci.h>
|
||||||
|
|
||||||
#include "sifive-prci.h"
|
#include "sifive-prci.h"
|
||||||
|
|
||||||
#define NUM_CLOCK_FU540 4
|
/* PRCI integration data for each WRPLL instance */
|
||||||
|
|
||||||
extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
|
static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
|
||||||
|
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
||||||
|
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
|
||||||
|
.disable_bypass = sifive_prci_coreclksel_use_corepll,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
|
||||||
|
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
|
||||||
|
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Linux clock framework integration */
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
|
||||||
|
.set_rate = sifive_prci_wrpll_set_rate,
|
||||||
|
.round_rate = sifive_prci_wrpll_round_rate,
|
||||||
|
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||||
|
.enable = sifive_prci_clock_enable,
|
||||||
|
.disable = sifive_prci_clock_disable,
|
||||||
|
.is_enabled = sifive_clk_is_enabled,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
|
||||||
|
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
|
||||||
|
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* List of clock controls provided by the PRCI */
|
||||||
|
static struct __prci_clock __prci_init_clocks_fu540[] = {
|
||||||
|
[FU540_PRCI_CLK_COREPLL] = {
|
||||||
|
.name = "corepll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
||||||
|
.pwd = &sifive_fu540_prci_corepll_data,
|
||||||
|
},
|
||||||
|
[FU540_PRCI_CLK_DDRPLL] = {
|
||||||
|
.name = "ddrpll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
|
||||||
|
.pwd = &sifive_fu540_prci_ddrpll_data,
|
||||||
|
},
|
||||||
|
[FU540_PRCI_CLK_GEMGXLPLL] = {
|
||||||
|
.name = "gemgxlpll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu540_prci_wrpll_clk_ops,
|
||||||
|
.pwd = &sifive_fu540_prci_gemgxlpll_data,
|
||||||
|
},
|
||||||
|
[FU540_PRCI_CLK_TLCLK] = {
|
||||||
|
.name = "tlclk",
|
||||||
|
.parent_name = "corepll",
|
||||||
|
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct prci_clk_desc prci_clk_fu540 = {
|
||||||
|
.clks = __prci_init_clocks_fu540,
|
||||||
|
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
|
||||||
|
};
|
||||||
|
|
||||||
#endif /* __SIFIVE_CLK_FU540_PRCI_H */
|
#endif /* __SIFIVE_CLK_FU540_PRCI_H */
|
||||||
|
|
|
||||||
|
|
@ -1,133 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2020-2022 SiFive, Inc.
|
|
||||||
* Copyright (C) 2020-2022 Zong Li
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/module.h>
|
|
||||||
|
|
||||||
#include <dt-bindings/clock/sifive-fu740-prci.h>
|
|
||||||
|
|
||||||
#include "sifive-prci.h"
|
|
||||||
|
|
||||||
/* PRCI integration data for each WRPLL instance */
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
|
|
||||||
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
|
||||||
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
|
|
||||||
.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
|
|
||||||
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
|
|
||||||
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
|
|
||||||
.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
|
|
||||||
.enable_bypass = sifive_prci_corepllsel_use_corepll,
|
|
||||||
.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
|
|
||||||
.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
|
|
||||||
.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
|
|
||||||
.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
|
|
||||||
.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
|
|
||||||
.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Linux clock framework integration */
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
|
|
||||||
.set_rate = sifive_prci_wrpll_set_rate,
|
|
||||||
.round_rate = sifive_prci_wrpll_round_rate,
|
|
||||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
|
||||||
.enable = sifive_prci_clock_enable,
|
|
||||||
.disable = sifive_prci_clock_disable,
|
|
||||||
.is_enabled = sifive_clk_is_enabled,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
|
|
||||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
|
|
||||||
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
|
|
||||||
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
|
|
||||||
.enable = sifive_prci_pcie_aux_clock_enable,
|
|
||||||
.disable = sifive_prci_pcie_aux_clock_disable,
|
|
||||||
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* List of clock controls provided by the PRCI */
|
|
||||||
struct __prci_clock __prci_init_clocks_fu740[] = {
|
|
||||||
[FU740_PRCI_CLK_COREPLL] = {
|
|
||||||
.name = "corepll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
|
||||||
.pwd = &sifive_fu740_prci_corepll_data,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_DDRPLL] = {
|
|
||||||
.name = "ddrpll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
|
|
||||||
.pwd = &sifive_fu740_prci_ddrpll_data,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_GEMGXLPLL] = {
|
|
||||||
.name = "gemgxlpll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
|
||||||
.pwd = &sifive_fu740_prci_gemgxlpll_data,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_DVFSCOREPLL] = {
|
|
||||||
.name = "dvfscorepll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
|
||||||
.pwd = &sifive_fu740_prci_dvfscorepll_data,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_HFPCLKPLL] = {
|
|
||||||
.name = "hfpclkpll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
|
||||||
.pwd = &sifive_fu740_prci_hfpclkpll_data,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_CLTXPLL] = {
|
|
||||||
.name = "cltxpll",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
|
||||||
.pwd = &sifive_fu740_prci_cltxpll_data,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_TLCLK] = {
|
|
||||||
.name = "tlclk",
|
|
||||||
.parent_name = "corepll",
|
|
||||||
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_PCLK] = {
|
|
||||||
.name = "pclk",
|
|
||||||
.parent_name = "hfpclkpll",
|
|
||||||
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
|
|
||||||
},
|
|
||||||
[FU740_PRCI_CLK_PCIE_AUX] = {
|
|
||||||
.name = "pcie_aux",
|
|
||||||
.parent_name = "hfclk",
|
|
||||||
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
@ -1,17 +1,139 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
/*
|
/*
|
||||||
* Copyright (C) 2020 SiFive, Inc.
|
* Copyright (C) 2020-2021 SiFive, Inc.
|
||||||
* Zong Li
|
* Copyright (C) 2020-2021 Zong Li
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __SIFIVE_CLK_FU740_PRCI_H
|
#ifndef __SIFIVE_CLK_FU740_PRCI_H
|
||||||
#define __SIFIVE_CLK_FU740_PRCI_H
|
#define __SIFIVE_CLK_FU740_PRCI_H
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
|
||||||
|
#include <dt-bindings/clock/sifive-fu740-prci.h>
|
||||||
|
|
||||||
#include "sifive-prci.h"
|
#include "sifive-prci.h"
|
||||||
|
|
||||||
#define NUM_CLOCK_FU740 9
|
/* PRCI integration data for each WRPLL instance */
|
||||||
|
|
||||||
extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
|
static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
|
||||||
|
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
|
||||||
|
.enable_bypass = sifive_prci_coreclksel_use_hfclk,
|
||||||
|
.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
|
||||||
|
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
|
||||||
|
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
|
||||||
|
.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
|
||||||
|
.enable_bypass = sifive_prci_corepllsel_use_corepll,
|
||||||
|
.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
|
||||||
|
.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
|
||||||
|
.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
|
||||||
|
.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
|
||||||
|
.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
|
||||||
|
.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Linux clock framework integration */
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
|
||||||
|
.set_rate = sifive_prci_wrpll_set_rate,
|
||||||
|
.round_rate = sifive_prci_wrpll_round_rate,
|
||||||
|
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||||
|
.enable = sifive_prci_clock_enable,
|
||||||
|
.disable = sifive_prci_clock_disable,
|
||||||
|
.is_enabled = sifive_clk_is_enabled,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
|
||||||
|
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
|
||||||
|
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
|
||||||
|
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
|
||||||
|
.enable = sifive_prci_pcie_aux_clock_enable,
|
||||||
|
.disable = sifive_prci_pcie_aux_clock_disable,
|
||||||
|
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* List of clock controls provided by the PRCI */
|
||||||
|
static struct __prci_clock __prci_init_clocks_fu740[] = {
|
||||||
|
[FU740_PRCI_CLK_COREPLL] = {
|
||||||
|
.name = "corepll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||||
|
.pwd = &sifive_fu740_prci_corepll_data,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_DDRPLL] = {
|
||||||
|
.name = "ddrpll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
|
||||||
|
.pwd = &sifive_fu740_prci_ddrpll_data,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_GEMGXLPLL] = {
|
||||||
|
.name = "gemgxlpll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||||
|
.pwd = &sifive_fu740_prci_gemgxlpll_data,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_DVFSCOREPLL] = {
|
||||||
|
.name = "dvfscorepll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||||
|
.pwd = &sifive_fu740_prci_dvfscorepll_data,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_HFPCLKPLL] = {
|
||||||
|
.name = "hfpclkpll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||||
|
.pwd = &sifive_fu740_prci_hfpclkpll_data,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_CLTXPLL] = {
|
||||||
|
.name = "cltxpll",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||||
|
.pwd = &sifive_fu740_prci_cltxpll_data,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_TLCLK] = {
|
||||||
|
.name = "tlclk",
|
||||||
|
.parent_name = "corepll",
|
||||||
|
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_PCLK] = {
|
||||||
|
.name = "pclk",
|
||||||
|
.parent_name = "hfpclkpll",
|
||||||
|
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
|
||||||
|
},
|
||||||
|
[FU740_PRCI_CLK_PCIE_AUX] = {
|
||||||
|
.name = "pcie_aux",
|
||||||
|
.parent_name = "hfclk",
|
||||||
|
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
static const struct prci_clk_desc prci_clk_fu740 = {
|
static const struct prci_clk_desc prci_clk_fu740 = {
|
||||||
.clks = __prci_init_clocks_fu740,
|
.clks = __prci_init_clocks_fu740,
|
||||||
|
|
|
||||||
|
|
@ -12,11 +12,6 @@
|
||||||
#include "fu540-prci.h"
|
#include "fu540-prci.h"
|
||||||
#include "fu740-prci.h"
|
#include "fu740-prci.h"
|
||||||
|
|
||||||
static const struct prci_clk_desc prci_clk_fu540 = {
|
|
||||||
.clks = __prci_init_clocks_fu540,
|
|
||||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Private functions
|
* Private functions
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
Загрузка…
Ссылка в новой задаче