[media] dib8096: enhancement
The intend of this patch is to improve the support of the dib8096. The PLL parameters are not automatically computed. The limit to set/unset external diode for attenuation has been updated. The TFE8096P board is using the new I2C API. Signed-off-by: Olivier Grenie <olivier.grenie@parrot.com> Signed-off-by: Patrick Boettcher <patrick.boettcher@parrot.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Olivier Grenie
Mauro Carvalho Chehab
Родитель
aedabf7a54
Коммит
5e9c85d983
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@ -1431,13 +1431,22 @@ static int dib8090_get_adc_power(struct dvb_frontend *fe)
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return dib8000_get_adc_power(fe, 1);
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}
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static void dib8090_agc_control(struct dvb_frontend *fe, u8 restart)
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{
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deb_info("AGC control callback: %i\n", restart);
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dib0090_dcc_freq(fe, restart);
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if (restart == 0) /* before AGC startup */
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dib0090_set_dc_servo(fe, 1);
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}
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static struct dib8000_config dib809x_dib8000_config[2] = {
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{
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.output_mpeg2_in_188_bytes = 1,
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.agc_config_count = 2,
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.agc = dib8090_agc_config,
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.agc_control = dib0090_dcc_freq,
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.agc_control = dib8090_agc_control,
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.pll = &dib8090_pll_config_12mhz,
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.tuner_is_baseband = 1,
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@ -1456,7 +1465,7 @@ static struct dib8000_config dib809x_dib8000_config[2] = {
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.agc_config_count = 2,
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.agc = dib8090_agc_config,
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.agc_control = dib0090_dcc_freq,
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.agc_control = dib8090_agc_control,
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.pll = &dib8090_pll_config_12mhz,
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.tuner_is_baseband = 1,
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@ -1504,28 +1513,89 @@ static struct dib0090_config dib809x_dib0090_config = {
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.fref_clock_ratio = 6,
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};
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static u8 dib8090_compute_pll_parameters(struct dvb_frontend *fe)
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{
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u8 optimal_pll_ratio = 20;
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u32 freq_adc, ratio, rest, max = 0;
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u8 pll_ratio;
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for (pll_ratio = 17; pll_ratio <= 20; pll_ratio++) {
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freq_adc = 12 * pll_ratio * (1 << 8) / 16;
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ratio = ((fe->dtv_property_cache.frequency / 1000) * (1 << 8) / 1000) / freq_adc;
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rest = ((fe->dtv_property_cache.frequency / 1000) * (1 << 8) / 1000) - ratio * freq_adc;
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if (rest > freq_adc / 2)
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rest = freq_adc - rest;
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deb_info("PLL ratio=%i rest=%i\n", pll_ratio, rest);
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if ((rest > max) && (rest > 717)) {
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optimal_pll_ratio = pll_ratio;
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max = rest;
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}
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}
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deb_info("optimal PLL ratio=%i\n", optimal_pll_ratio);
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return optimal_pll_ratio;
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}
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static int dib8096_set_param_override(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct dvb_usb_adapter *adap = fe->dvb->priv;
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struct dib0700_adapter_state *state = adap->priv;
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u8 band = BAND_OF_FREQUENCY(p->frequency/1000);
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u16 target;
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u8 pll_ratio, band = BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000);
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u16 target, ltgain, rf_gain_limit;
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u32 timf;
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int ret = 0;
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enum frontend_tune_state tune_state = CT_SHUTDOWN;
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u16 ltgain, rf_gain_limit;
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switch (band) {
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default:
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deb_info("Warning : Rf frequency (%iHz) is not in the supported range, using VHF switch ", fe->dtv_property_cache.frequency);
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case BAND_VHF:
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dib8000_set_gpio(fe, 3, 0, 1);
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break;
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case BAND_UHF:
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dib8000_set_gpio(fe, 3, 0, 0);
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break;
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}
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ret = state->set_param_save(fe);
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if (ret < 0)
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return ret;
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target = (dib0090_get_wbd_target(fe) * 8 * 18 / 33 + 1) / 2;
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dib8000_set_wbd_ref(fe, target);
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if (fe->dtv_property_cache.bandwidth_hz != 6000000) {
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deb_info("only 6MHz bandwidth is supported\n");
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return -EINVAL;
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}
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/** Update PLL if needed ratio **/
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dib8000_update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
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/** Get optimize PLL ratio to remove spurious **/
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pll_ratio = dib8090_compute_pll_parameters(fe);
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if (pll_ratio == 17)
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timf = 21387946;
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else if (pll_ratio == 18)
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timf = 20199727;
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else if (pll_ratio == 19)
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timf = 19136583;
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else
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timf = 18179756;
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/** Update ratio **/
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dib8000_update_pll(fe, &dib8090_pll_config_12mhz, fe->dtv_property_cache.bandwidth_hz / 1000, pll_ratio);
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dib8000_ctrl_timf(fe, DEMOD_TIMF_SET, timf);
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if (band != BAND_CBAND) {
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/* dib0090_get_wbd_target is returning any possible temperature compensated wbd-target */
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target = (dib0090_get_wbd_target(fe) * 8 * 18 / 33 + 1) / 2;
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dib8000_set_wbd_ref(fe, target);
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}
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if (band == BAND_CBAND) {
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deb_info("tuning in CBAND - soft-AGC startup\n");
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dib0090_set_tune_state(fe, CT_AGC_START);
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do {
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ret = dib0090_gain_control(fe);
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msleep(ret);
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@ -1534,14 +1604,17 @@ static int dib8096_set_param_override(struct dvb_frontend *fe)
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dib8000_set_gpio(fe, 6, 0, 1);
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else if (tune_state == CT_AGC_STEP_1) {
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dib0090_get_current_gain(fe, NULL, NULL, &rf_gain_limit, <gain);
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if (rf_gain_limit == 0)
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if (rf_gain_limit < 2000) /* activate the external attenuator in case of very high input power */
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dib8000_set_gpio(fe, 6, 0, 0);
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}
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} while (tune_state < CT_AGC_STOP);
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deb_info("switching to PWM AGC\n");
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dib0090_pwm_gain_reset(fe);
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dib8000_pwm_agc_reset(fe);
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dib8000_set_tune_state(fe, CT_DEMOD_START);
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} else {
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/* for everything else than CBAND we are using standard AGC */
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deb_info("not tuning in CBAND - standard AGC startup\n");
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dib0090_pwm_gain_reset(fe);
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}
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@ -1814,21 +1887,92 @@ struct dibx090p_adc {
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u32 pll_prediv; /* New loopdiv */
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};
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struct dibx090p_adc dib8090p_adc_tab[] = {
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{ 50000, 17043521, 16, 3}, /* 64 MHz */
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{878000, 20199729, 9, 1}, /* 60 MHz */
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{0xffffffff, 0, 0, 0}, /* 60 MHz */
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struct dibx090p_best_adc {
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u32 timf;
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u32 pll_loopdiv;
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u32 pll_prediv;
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};
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static int dib8096p_get_best_sampling(struct dvb_frontend *fe, struct dibx090p_best_adc *adc)
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{
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u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;
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u16 xtal = 12000;
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u16 fcp_min = 1900; /* PLL, Minimum Frequency of phase comparator (KHz) */
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u16 fcp_max = 20000; /* PLL, Maximum Frequency of phase comparator (KHz) */
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u32 fmem_max = 140000; /* 140MHz max SDRAM freq */
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u32 fdem_min = 66000;
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u32 fcp = 0, fs = 0, fdem = 0, fmem = 0;
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u32 harmonic_id = 0;
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adc->timf = 0;
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adc->pll_loopdiv = loopdiv;
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adc->pll_prediv = prediv;
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deb_info("bandwidth = %d", fe->dtv_property_cache.bandwidth_hz);
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/* Find Min and Max prediv */
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while ((xtal / max_prediv) >= fcp_min)
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max_prediv++;
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max_prediv--;
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min_prediv = max_prediv;
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while ((xtal / min_prediv) <= fcp_max) {
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min_prediv--;
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if (min_prediv == 1)
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break;
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}
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deb_info("MIN prediv = %d : MAX prediv = %d", min_prediv, max_prediv);
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min_prediv = 1;
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for (prediv = min_prediv; prediv < max_prediv; prediv++) {
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fcp = xtal / prediv;
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if (fcp > fcp_min && fcp < fcp_max) {
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for (loopdiv = 1; loopdiv < 64; loopdiv++) {
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fmem = ((xtal/prediv) * loopdiv);
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fdem = fmem / 2;
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fs = fdem / 4;
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/* test min/max system restrictions */
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if ((fdem >= fdem_min) && (fmem <= fmem_max) && (fs >= fe->dtv_property_cache.bandwidth_hz / 1000)) {
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spur = 0;
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/* test fs harmonics positions */
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for (harmonic_id = (fe->dtv_property_cache.frequency / (1000 * fs)); harmonic_id <= ((fe->dtv_property_cache.frequency / (1000 * fs)) + 1); harmonic_id++) {
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if (((fs * harmonic_id) >= (fe->dtv_property_cache.frequency / 1000 - (fe->dtv_property_cache.bandwidth_hz / 2000))) && ((fs * harmonic_id) <= (fe->dtv_property_cache.frequency / 1000 + (fe->dtv_property_cache.bandwidth_hz / 2000)))) {
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spur = 1;
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break;
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}
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}
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if (!spur) {
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adc->pll_loopdiv = loopdiv;
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adc->pll_prediv = prediv;
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adc->timf = (4260880253U / fdem) * (1 << 8);
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adc->timf += ((4260880253U % fdem) << 8) / fdem;
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deb_info("RF %6d; BW %6d; Xtal %6d; Fmem %6d; Fdem %6d; Fs %6d; Prediv %2d; Loopdiv %2d; Timf %8d;", fe->dtv_property_cache.frequency, fe->dtv_property_cache.bandwidth_hz, xtal, fmem, fdem, fs, prediv, loopdiv, adc->timf);
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break;
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}
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}
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}
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}
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if (!spur)
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break;
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}
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if (adc->pll_loopdiv == 0 && adc->pll_prediv == 0)
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return -EINVAL;
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return 0;
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}
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static int dib8096p_agc_startup(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct dvb_usb_adapter *adap = fe->dvb->priv;
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struct dib0700_adapter_state *state = adap->priv;
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struct dibx000_bandwidth_config pll;
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struct dibx090p_best_adc adc;
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u16 target;
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int better_sampling_freq = 0, ret;
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struct dibx090p_adc *adc_table = &dib8090p_adc_tab[0];
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int ret;
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ret = state->set_param_save(fe);
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if (ret < 0)
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@ -1841,23 +1985,27 @@ static int dib8096p_agc_startup(struct dvb_frontend *fe)
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target = (dib0090_get_wbd_target(fe) * 8 + 1) / 2;
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dib8000_set_wbd_ref(fe, target);
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if (dib8096p_get_best_sampling(fe, &adc) == 0) {
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pll.pll_ratio = adc.pll_loopdiv;
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pll.pll_prediv = adc.pll_prediv;
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while (p->frequency / 1000 > adc_table->freq) {
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better_sampling_freq = 1;
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adc_table++;
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}
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if ((adc_table->freq != 0xffffffff) && better_sampling_freq) {
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pll.pll_ratio = adc_table->pll_loopdiv;
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pll.pll_prediv = adc_table->pll_prediv;
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dib0700_set_i2c_speed(adap->dev, 200);
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dib8000_update_pll(fe, &pll, fe->dtv_property_cache.bandwidth_hz / 1000, 0);
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dib8000_ctrl_timf(fe, DEMOD_TIMF_SET, adc_table->timf);
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dib8000_ctrl_timf(fe, DEMOD_TIMF_SET, adc.timf);
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dib0700_set_i2c_speed(adap->dev, 1000);
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}
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return 0;
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}
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static int tfe8096p_frontend_attach(struct dvb_usb_adapter *adap)
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{
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struct dib0700_state *st = adap->dev->priv;
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u32 fw_version;
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dib0700_get_version(adap->dev, NULL, NULL, &fw_version, NULL);
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if (fw_version >= 0x10200)
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st->fw_use_new_i2c_api = 1;
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dib0700_set_gpio(adap->dev, GPIO6, GPIO_OUT, 1);
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msleep(20);
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dib0700_set_gpio(adap->dev, GPIO9, GPIO_OUT, 1);
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@ -2242,13 +2390,7 @@ static int nim9090md_tuner_attach(struct dvb_usb_adapter *adap)
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}
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/* NIM7090 */
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struct dib7090p_best_adc {
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u32 timf;
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u32 pll_loopdiv;
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u32 pll_prediv;
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};
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static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dib7090p_best_adc *adc)
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static int dib7090p_get_best_sampling(struct dvb_frontend *fe , struct dibx090p_best_adc *adc)
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{
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u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1;
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@ -2327,7 +2469,7 @@ static int dib7090_agc_startup(struct dvb_frontend *fe)
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struct dib0700_adapter_state *state = adap->priv;
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struct dibx000_bandwidth_config pll;
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u16 target;
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struct dib7090p_best_adc adc;
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struct dibx090p_best_adc adc;
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int ret;
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ret = state->set_param_save(fe);
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