This pull request contains cleanups and
non-urgent fixes for DaVinci McASP platform support code. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJVCXGLAAoJEGFBu2jqvgRNzbEP/jR5Idh7L9gbJRhbqjgjOMbD zaQOxmiZLoLNg2f7QlT2nIT7O2iqQwYrhlTKLjZJN3X7QokUDPcxPfddRlZONriX E+PI6vTQ6jbQqVRz3rHkaerOGduC5ZhQtVbdXqJyEZgCVUHfV8L9hEtZWhS03y20 0bQAa+3Qwn/gLpsfpQFLFDOudjl47OxlNQjDyON83iGtdlgrOmDkCHJlCq4uNFFF IiIHgHMhrIxe1RXHhRSMb+fNQYXArS7soL+vtNkJxjtrZuEPA1MC9Yk8Tl4iVQNO 4AaAdAA8nBjXgOrWwXfs/Le824sDGGVyaXuiFu/zUE6qGJGHyEC0r6M6fAPBtSlx DLuvwFfdV/CwNS//O6ZxL5TsKtIpbseoIENAILEzmbi10kvL2iGFb1crS/3evmpr eRRb8dTU5HH+isiUb/AczwFJrQA5G+m4Mh0o0lrmaqj50E4NyJYTtlkfz80DI3e7 h0TegyRkcBYE6GuI1cy5U4zZETCJZ1gnDz4TIXggDzHrKHJ1ULbrSNrJ9BN2Ewkx chPlFsUAiRyBS+uiHHumbcF0GusWqW6Q9x/lNTYMhAGi9D061lTfYbLISYdmdVJV FBb2JD9ft4tBw7yYtMdNait5p6yfHvGiS3UlwzsA5CmXGoFnUTLNg8BO6l2/pVTq u1SWTmvC8bJ/vJ/NqB4A =xRKx -----END PGP SIGNATURE----- Merge tag 'davinci-for-v4.1/mcasp' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/cleanup Merge "DaVinci McASP changes for v4.1" from Sekhar Nori: This pull request contains cleanups and non-urgent fixes for DaVinci McASP platform support code. * tag 'davinci-for-v4.1/mcasp' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: dm646x: Add interrupt resource for McASPs ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x ARM: davinci: dm646x: Clean up the McASP DMA resources ARM: davinci: devices-da8xx: Add support for McASP2 on da830 ARM: davinci: devices-da8xx: Clean up and correct the McASP device creation ARM: davinci: devices-da8xx: Add interrupt resource to McASP structs ARM: davinci: devices-da8xx: Add resource name for the McASP DMA request Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Коммит
5ec5e792fe
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@ -21,6 +21,9 @@
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/* Bases of da830 McASP1 register banks */
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/* Bases of da830 McASP1 register banks */
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#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
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#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
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/* Bases of da830 McASP2 register banks */
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#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000
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/* EDMA channels of dm644x and dm355 */
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/* EDMA channels of dm644x and dm355 */
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#define DAVINCI_DMA_ASP0_TX 2
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#define DAVINCI_DMA_ASP0_TX 2
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#define DAVINCI_DMA_ASP0_RX 3
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#define DAVINCI_DMA_ASP0_RX 3
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@ -40,6 +43,10 @@
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#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
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#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
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#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
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#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
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/* EDMA channels of da830 McASP2 */
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#define DAVINCI_DA830_DMA_MCASP2_AREVT 4
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#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
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/* Interrupts */
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/* Interrupts */
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#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
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#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
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#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
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#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
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@ -463,16 +463,23 @@ static struct resource da830_mcasp1_resources[] = {
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},
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},
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/* TX event */
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/* TX event */
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{
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{
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.name = "tx",
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.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
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.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
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.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
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.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_DMA,
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},
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},
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/* RX event */
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/* RX event */
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{
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{
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.name = "rx",
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.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
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.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
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.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
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.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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.name = "common",
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.start = IRQ_DA8XX_MCASPINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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};
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static struct platform_device da830_mcasp1_device = {
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static struct platform_device da830_mcasp1_device = {
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@ -482,6 +489,41 @@ static struct platform_device da830_mcasp1_device = {
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.resource = da830_mcasp1_resources,
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.resource = da830_mcasp1_resources,
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};
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};
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static struct resource da830_mcasp2_resources[] = {
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{
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.name = "mpu",
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.start = DAVINCI_DA830_MCASP2_REG_BASE,
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.end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
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.flags = IORESOURCE_MEM,
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},
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/* TX event */
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{
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.name = "tx",
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.start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
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.end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
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.flags = IORESOURCE_DMA,
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},
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/* RX event */
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{
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.name = "rx",
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.start = DAVINCI_DA830_DMA_MCASP2_AREVT,
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.end = DAVINCI_DA830_DMA_MCASP2_AREVT,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "common",
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.start = IRQ_DA8XX_MCASPINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device da830_mcasp2_device = {
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.name = "davinci-mcasp",
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.id = 2,
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.num_resources = ARRAY_SIZE(da830_mcasp2_resources),
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.resource = da830_mcasp2_resources,
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};
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static struct resource da850_mcasp_resources[] = {
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static struct resource da850_mcasp_resources[] = {
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{
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{
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.name = "mpu",
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.name = "mpu",
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@ -491,16 +533,23 @@ static struct resource da850_mcasp_resources[] = {
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},
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},
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/* TX event */
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/* TX event */
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{
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{
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.name = "tx",
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.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
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.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
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.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
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.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_DMA,
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},
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},
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/* RX event */
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/* RX event */
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{
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{
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.name = "rx",
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.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
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.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
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.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
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.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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.name = "common",
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.start = IRQ_DA8XX_MCASPINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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};
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static struct platform_device da850_mcasp_device = {
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static struct platform_device da850_mcasp_device = {
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@ -512,14 +561,31 @@ static struct platform_device da850_mcasp_device = {
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void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
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void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
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{
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{
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/* DA830/OMAP-L137 has 3 instances of McASP */
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struct platform_device *pdev;
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if (cpu_is_davinci_da830() && id == 1) {
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da830_mcasp1_device.dev.platform_data = pdata;
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switch (id) {
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platform_device_register(&da830_mcasp1_device);
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case 0:
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} else if (cpu_is_davinci_da850()) {
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/* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
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da850_mcasp_device.dev.platform_data = pdata;
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pdev = &da850_mcasp_device;
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platform_device_register(&da850_mcasp_device);
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break;
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case 1:
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/* Valid for DA830/OMAP-L137 only */
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if (!cpu_is_davinci_da830())
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return;
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pdev = &da830_mcasp1_device;
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break;
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case 2:
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/* Valid for DA830/OMAP-L137 only */
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if (!cpu_is_davinci_da830())
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return;
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pdev = &da830_mcasp2_device;
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break;
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default:
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return;
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}
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}
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pdev->dev.platform_data = pdata;
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platform_device_register(pdev);
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}
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}
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static struct resource da8xx_pruss_resources[] = {
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static struct resource da8xx_pruss_resources[] = {
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@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_DM646X_EMACMISCINT] = 7,
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[IRQ_DM646X_EMACMISCINT] = 7,
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[IRQ_DM646X_MCASP0TXINT] = 7,
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[IRQ_DM646X_MCASP0TXINT] = 7,
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[IRQ_DM646X_MCASP0RXINT] = 7,
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[IRQ_DM646X_MCASP0RXINT] = 7,
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[IRQ_AEMIFINT] = 7,
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[IRQ_DM646X_RESERVED_3] = 7,
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[IRQ_DM646X_RESERVED_3] = 7,
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[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
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[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
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[IRQ_TINT0_TINT34] = 7, /* clocksource */
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[IRQ_TINT0_TINT34] = 7, /* clocksource */
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@ -610,19 +609,31 @@ static struct resource dm646x_mcasp0_resources[] = {
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.end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
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.end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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/* first TX, then RX */
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{
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{
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.name = "tx",
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.start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
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.start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
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.end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
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.end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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{
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.name = "rx",
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.start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
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.start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
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.end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
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.end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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.name = "tx",
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.start = IRQ_DM646X_MCASP0TXINT,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = IRQ_DM646X_MCASP0RXINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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};
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/* DIT mode only, rx is not supported */
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static struct resource dm646x_mcasp1_resources[] = {
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static struct resource dm646x_mcasp1_resources[] = {
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{
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{
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.name = "mpu",
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.name = "mpu",
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@ -630,17 +641,16 @@ static struct resource dm646x_mcasp1_resources[] = {
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.end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
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.end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
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.flags = IORESOURCE_MEM,
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.flags = IORESOURCE_MEM,
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},
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},
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/* DIT mode, only TX event */
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{
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{
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.name = "tx",
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.start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
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.start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
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.end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
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.end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_DMA,
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},
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},
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/* DIT mode, dummy entry */
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{
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{
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.start = -1,
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.name = "tx",
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.end = -1,
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.start = IRQ_DM646X_MCASP1TXINT,
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.flags = IORESOURCE_DMA,
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.flags = IORESOURCE_IRQ,
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},
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},
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};
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};
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@ -129,8 +129,8 @@
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#define IRQ_DM646X_EMACMISCINT 27
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#define IRQ_DM646X_EMACMISCINT 27
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#define IRQ_DM646X_MCASP0TXINT 28
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#define IRQ_DM646X_MCASP0TXINT 28
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#define IRQ_DM646X_MCASP0RXINT 29
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#define IRQ_DM646X_MCASP0RXINT 29
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#define IRQ_DM646X_MCASP1TXINT 30
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#define IRQ_DM646X_RESERVED_3 31
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#define IRQ_DM646X_RESERVED_3 31
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#define IRQ_DM646X_MCASP1TXINT 32
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#define IRQ_DM646X_VLQINT 38
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#define IRQ_DM646X_VLQINT 38
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#define IRQ_DM646X_UARTINT2 42
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#define IRQ_DM646X_UARTINT2 42
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#define IRQ_DM646X_SPINT0 43
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#define IRQ_DM646X_SPINT0 43
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