drm fixes for 5.17-rc6
core: - edid: Always set RGB444 tegra: - tegra186 suspend/resume fixes - syncpoint wait fix - build warning fix - eDP on older devices fix amdgpu: - Display FP fix - PCO powergating fix - RDNA2 OEM SKU stability fixes - Display PSR fix - PCI ASPM fix - Display link encoder fix for TEST_COMMIT - Raven2 suspend/resume fix - Fix a regression in virtual display support - GPUVM eviction fix i915: - Fix QGV handling on ADL-P+ - Fix bw atomic check when switching between SAGV vs. no SAGV - Disconnect PHYs left connected by BIOS on disabled ports - Fix SAVG to no SAGV transitions on TGL+ - Print PHY name properly on calibration error (DG2) imx: - dcss: Select GEM CMA helpers radeon: - Fix some variables's type vc4: - Fix codec cleanup - Fix PM reference counting -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmIYDakACgkQDHTzWXnE hr5BTRAAhBaMBWPNMq7lPj/FfgivQ2/DmWZSC8J+yKVZNPR3ce87i13YJun0BLIa MoymnuRKSVSeCOsu0LcNwHjOHFhhn+d7U8e2pT1Q2ellWWW0dQEqU37znq5iAZO+ 2U05AEk3DguRPEPxf1RUTZWMYb247z5iZLtrrcIFWyjUgcNtA15GRSswutQM9xCf DVMMrPR2XHIpn+O+PIutH4ykNPK9h+K6ZRN/W4c8WzsYk0cW+d/aFhMF/IpSqGeG XzIjzy1TzetDDv0y20hGyIASSEXrIw2akhOBsHXJEsjOjGbCRYVt+DmAr8ku7y04 YZWrOutbEf4igczMGfeJxqUWGT5LtB9hR7EdTY8LtoCOzwz4IxB0UuaXIq+KVlIv tyY4DZmWRfTDwa0ZFAqZkkhepJB4kT1y0TGf9rXvYzW647hB8k4jGEA7VBAGhtMB 3BOVGsQyCM63LQ5bxJYor787DWGyGtai61QSXa5J2QPjMEKFmYzY8qkvZB38zZsJ ZEmGyNOeMXIy7Zj2+sq2ewLwkOjEQQwDUesEgAkNP+TBruvuIsCAHYHQQ4/4PpHH d437ZYJf7F8/ktPQw+Ri6l4i5QRsjeRj52omgAf9/qjoG4KaaEM8tI4yg9/apIiI EiL/wGQ0XSxjWBVP/C541fU4lfYG8eXjWmMo7R2Gc/A1YfKEKFs= =V5aD -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2022-02-25' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Regular drm fixes pull, i915, amdgpu and tegra mostly, all pretty small. core: - edid: Always set RGB444 tegra: - tegra186 suspend/resume fixes - syncpoint wait fix - build warning fix - eDP on older devices fix amdgpu: - Display FP fix - PCO powergating fix - RDNA2 OEM SKU stability fixes - Display PSR fix - PCI ASPM fix - Display link encoder fix for TEST_COMMIT - Raven2 suspend/resume fix - Fix a regression in virtual display support - GPUVM eviction fix i915: - Fix QGV handling on ADL-P+ - Fix bw atomic check when switching between SAGV vs. no SAGV - Disconnect PHYs left connected by BIOS on disabled ports - Fix SAVG to no SAGV transitions on TGL+ - Print PHY name properly on calibration error (DG2) imx: - dcss: Select GEM CMA helpers radeon: - Fix some variables's type vc4: - Fix codec cleanup - Fix PM reference counting" * tag 'drm-fixes-2022-02-25' of git://anongit.freedesktop.org/drm/drm: (24 commits) drm/amdgpu: check vm ready by amdgpu_vm->evicting flag drm/amdgpu: bypass tiling flag check in virtual display case (v2) Revert "drm/amdgpu: add modifiers in amdgpu_vkms_plane_init()" drm/amdgpu: do not enable asic reset for raven2 drm/amd/display: Fix stream->link_enc unassigned during stream removal drm/amd: Check if ASPM is enabled from PCIe subsystem drm/edid: Always set RGB444 drm/tegra: dpaux: Populate AUX bus drm/radeon: fix variable type drm/amd/display: For vblank_disable_immediate, check PSR is really used drm/amd/pm: fix some OEM SKU specific stability issues drm/amdgpu: disable MMHUB PG for Picasso drm/amd/display: Protect update_bw_bounding_box FPU code. drm/i915/dg2: Print PHY name properly on calibration error drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV drm/i915: Correctly populate use_sagv_wm for all pipes drm/i915: Disconnect PHYs left connected by BIOS on disabled ports drm/i915: Widen the QGV point mask drm/imx/dcss: i.MX8MQ DCSS select DRM_GEM_CMA_HELPER drm/vc4: crtc: Fix runtime_pm reference counting ...
This commit is contained in:
Linus Torvalds
Коммит
5ee3d0015a
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@ -1141,7 +1141,7 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev,
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if (ret)
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return ret;
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if (!dev->mode_config.allow_fb_modifiers) {
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if (!dev->mode_config.allow_fb_modifiers && !adev->enable_virtual_display) {
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drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
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"GFX9+ requires FB check based on format modifier\n");
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ret = check_tiling_flags_gfx6(rfb);
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@ -2011,6 +2011,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
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return -ENODEV;
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}
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if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
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amdgpu_aspm = 0;
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if (amdgpu_virtual_display ||
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amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
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supports_atomic = true;
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@ -391,7 +391,6 @@ static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev,
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int index)
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{
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struct drm_plane *plane;
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uint64_t modifiers[] = {DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID};
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int ret;
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plane = kzalloc(sizeof(*plane), GFP_KERNEL);
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@ -402,7 +401,7 @@ static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev,
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&amdgpu_vkms_plane_funcs,
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amdgpu_vkms_formats,
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ARRAY_SIZE(amdgpu_vkms_formats),
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modifiers, type, NULL);
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NULL, type, NULL);
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if (ret) {
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kfree(plane);
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return ERR_PTR(ret);
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@ -768,11 +768,16 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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* Check if all VM PDs/PTs are ready for updates
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*
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* Returns:
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* True if eviction list is empty.
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* True if VM is not evicting.
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*/
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bool amdgpu_vm_ready(struct amdgpu_vm *vm)
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{
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return list_empty(&vm->evicted);
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bool ret;
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amdgpu_vm_eviction_lock(vm);
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ret = !vm->evicting;
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amdgpu_vm_eviction_unlock(vm);
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return ret;
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}
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/**
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@ -619,8 +619,8 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
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static int soc15_asic_reset(struct amdgpu_device *adev)
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{
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/* original raven doesn't have full asic reset */
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if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
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!(adev->apu_flags & AMD_APU_IS_RAVEN2))
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if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
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(adev->apu_flags & AMD_APU_IS_RAVEN2))
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return 0;
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switch (soc15_asic_reset_method(adev)) {
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@ -1114,8 +1114,11 @@ static int soc15_common_early_init(void *handle)
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AMD_CG_SUPPORT_SDMA_LS |
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AMD_CG_SUPPORT_VCN_MGCG;
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/*
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* MMHUB PG needs to be disabled for Picasso for
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* stability reasons.
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*/
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adev->pg_flags = AMD_PG_SUPPORT_SDMA |
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AMD_PG_SUPPORT_MMHUB |
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AMD_PG_SUPPORT_VCN;
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} else {
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adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
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@ -4256,6 +4256,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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}
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#endif
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/* Disable vblank IRQs aggressively for power-saving. */
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adev_to_drm(adev)->vblank_disable_immediate = true;
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/* loops over all connectors on the board */
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for (i = 0; i < link_cnt; i++) {
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struct dc_link *link = NULL;
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@ -4301,19 +4304,17 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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update_connector_ext_caps(aconnector);
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if (psr_feature_enabled)
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amdgpu_dm_set_psr_caps(link);
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/* TODO: Fix vblank control helpers to delay PSR entry to allow this when
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* PSR is also supported.
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*/
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if (link->psr_settings.psr_feature_enabled)
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adev_to_drm(adev)->vblank_disable_immediate = false;
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}
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}
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/*
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* Disable vblank IRQs aggressively for power-saving.
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*
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* TODO: Fix vblank control helpers to delay PSR entry to allow this when PSR
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* is also supported.
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*/
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adev_to_drm(adev)->vblank_disable_immediate = !psr_feature_enabled;
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/* Software is initialized. Now we can register interrupt handlers. */
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switch (adev->asic_type) {
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#if defined(CONFIG_DRM_AMD_DC_SI)
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@ -473,8 +473,10 @@ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
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clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
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/* Refresh bounding box */
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DC_FP_START();
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clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
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clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
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DC_FP_END();
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}
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static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)
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@ -985,10 +985,13 @@ static bool dc_construct(struct dc *dc,
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goto fail;
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#ifdef CONFIG_DRM_AMD_DC_DCN
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dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
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#endif
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if (dc->res_pool->funcs->update_bw_bounding_box)
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if (dc->res_pool->funcs->update_bw_bounding_box) {
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DC_FP_START();
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dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
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DC_FP_END();
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}
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#endif
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/* Creation of current_state must occur after dc->dml
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* is initialized in dc_create_resource_pool because
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@ -1964,10 +1964,6 @@ enum dc_status dc_remove_stream_from_ctx(
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dc->res_pool,
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del_pipe->stream_res.stream_enc,
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false);
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/* Release link encoder from stream in new dc_state. */
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if (dc->res_pool->funcs->link_enc_unassign)
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dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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if (is_dp_128b_132b_signal(del_pipe)) {
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update_hpo_dp_stream_engine_usage(
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@ -421,6 +421,36 @@ static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
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return 0;
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}
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static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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uint32_t *board_reserved;
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uint16_t *freq_table_gfx;
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uint32_t i;
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/* Fix some OEM SKU specific stability issues */
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GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
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if ((adev->pdev->device == 0x73DF) &&
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(adev->pdev->revision == 0XC3) &&
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(adev->pdev->subsystem_device == 0x16C2) &&
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(adev->pdev->subsystem_vendor == 0x1043))
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board_reserved[0] = 1387;
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GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
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if ((adev->pdev->device == 0x73DF) &&
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(adev->pdev->revision == 0XC3) &&
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((adev->pdev->subsystem_device == 0x16C2) ||
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(adev->pdev->subsystem_device == 0x133C)) &&
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(adev->pdev->subsystem_vendor == 0x1043)) {
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for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
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if (freq_table_gfx[i] > 2500)
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freq_table_gfx[i] = 2500;
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}
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}
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return 0;
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}
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static int sienna_cichlid_setup_pptable(struct smu_context *smu)
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{
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int ret = 0;
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@ -441,7 +471,7 @@ static int sienna_cichlid_setup_pptable(struct smu_context *smu)
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if (ret)
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return ret;
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return ret;
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return sienna_cichlid_patch_pptable_quirk(smu);
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}
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static int sienna_cichlid_tables_init(struct smu_context *smu)
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|
|
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@ -5345,6 +5345,7 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
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if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
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return quirks;
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info->color_formats |= DRM_COLOR_FORMAT_RGB444;
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drm_parse_cea_ext(connector, edid);
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/*
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@ -5393,7 +5394,6 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
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DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
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connector->name, info->bpc);
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info->color_formats |= DRM_COLOR_FORMAT_RGB444;
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if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
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info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
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if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
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|
|
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@ -825,6 +825,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
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unsigned int max_bw_point = 0, max_bw = 0;
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unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
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unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
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bool changed = false;
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u32 mask = 0;
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/* FIXME earlier gens need some checks too */
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|
@ -868,6 +869,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
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new_bw_state->data_rate[crtc->pipe] = new_data_rate;
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new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
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|
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changed = true;
|
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drm_dbg_kms(&dev_priv->drm,
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"pipe %c data rate %u num active planes %u\n",
|
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pipe_name(crtc->pipe),
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|
|
@ -875,7 +878,19 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
|
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new_bw_state->num_active_planes[crtc->pipe]);
|
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}
|
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|
||||
if (!new_bw_state)
|
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old_bw_state = intel_atomic_get_old_bw_state(state);
|
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new_bw_state = intel_atomic_get_new_bw_state(state);
|
||||
|
||||
if (new_bw_state &&
|
||||
intel_can_enable_sagv(dev_priv, old_bw_state) !=
|
||||
intel_can_enable_sagv(dev_priv, new_bw_state))
|
||||
changed = true;
|
||||
|
||||
/*
|
||||
* If none of our inputs (data rates, number of active
|
||||
* planes, SAGV yes/no) changed then nothing to do here.
|
||||
*/
|
||||
if (!changed)
|
||||
return 0;
|
||||
|
||||
ret = intel_atomic_lock_global_state(&new_bw_state->base);
|
||||
|
|
@ -961,7 +976,6 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
|
|||
*/
|
||||
new_bw_state->qgv_points_mask = ~allowed_points & mask;
|
||||
|
||||
old_bw_state = intel_atomic_get_old_bw_state(state);
|
||||
/*
|
||||
* If the actual mask had changed we need to make sure that
|
||||
* the commits are serialized(in case this is a nomodeset, nonblocking)
|
||||
|
|
|
|||
|
|
@ -30,19 +30,19 @@ struct intel_bw_state {
|
|||
*/
|
||||
u8 pipe_sagv_reject;
|
||||
|
||||
/* bitmask of active pipes */
|
||||
u8 active_pipes;
|
||||
|
||||
/*
|
||||
* Current QGV points mask, which restricts
|
||||
* some particular SAGV states, not to confuse
|
||||
* with pipe_sagv_mask.
|
||||
*/
|
||||
u8 qgv_points_mask;
|
||||
u16 qgv_points_mask;
|
||||
|
||||
unsigned int data_rate[I915_MAX_PIPES];
|
||||
u8 num_active_planes[I915_MAX_PIPES];
|
||||
|
||||
/* bitmask of active pipes */
|
||||
u8 active_pipes;
|
||||
|
||||
int min_cdclk;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
|
|||
if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
|
||||
DG2_PHY_DP_TX_ACK_MASK, 25))
|
||||
DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
|
||||
phy);
|
||||
phy_name(phy));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -691,6 +691,8 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
|
|||
{
|
||||
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
||||
struct intel_encoder *encoder = &dig_port->base;
|
||||
intel_wakeref_t tc_cold_wref;
|
||||
enum intel_display_power_domain domain;
|
||||
int active_links = 0;
|
||||
|
||||
mutex_lock(&dig_port->tc_lock);
|
||||
|
|
@ -702,12 +704,11 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
|
|||
|
||||
drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_DISCONNECTED);
|
||||
drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
|
||||
|
||||
tc_cold_wref = tc_cold_block(dig_port, &domain);
|
||||
|
||||
dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
|
||||
if (active_links) {
|
||||
enum intel_display_power_domain domain;
|
||||
intel_wakeref_t tc_cold_wref = tc_cold_block(dig_port, &domain);
|
||||
|
||||
dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
|
||||
|
||||
if (!icl_tc_phy_is_connected(dig_port))
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"Port %s: PHY disconnected with %d active link(s)\n",
|
||||
|
|
@ -716,10 +717,23 @@ void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
|
|||
|
||||
dig_port->tc_lock_wakeref = tc_cold_block(dig_port,
|
||||
&dig_port->tc_lock_power_domain);
|
||||
|
||||
tc_cold_unblock(dig_port, domain, tc_cold_wref);
|
||||
} else {
|
||||
/*
|
||||
* TBT-alt is the default mode in any case the PHY ownership is not
|
||||
* held (regardless of the sink's connected live state), so
|
||||
* we'll just switch to disconnected mode from it here without
|
||||
* a note.
|
||||
*/
|
||||
if (dig_port->tc_mode != TC_PORT_TBT_ALT)
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"Port %s: PHY left in %s mode on disabled port, disconnecting it\n",
|
||||
dig_port->tc_port_name,
|
||||
tc_port_mode_name(dig_port->tc_mode));
|
||||
icl_tc_phy_disconnect(dig_port);
|
||||
}
|
||||
|
||||
tc_cold_unblock(dig_port, domain, tc_cold_wref);
|
||||
|
||||
drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n",
|
||||
dig_port->tc_port_name,
|
||||
tc_port_mode_name(dig_port->tc_mode));
|
||||
|
|
|
|||
|
|
@ -4029,6 +4029,17 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
|
||||
intel_can_enable_sagv(dev_priv, old_bw_state)) {
|
||||
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
|
||||
ret = intel_atomic_lock_global_state(&new_bw_state->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
for_each_new_intel_crtc_in_state(state, crtc,
|
||||
new_crtc_state, i) {
|
||||
struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
|
||||
|
|
@ -4044,17 +4055,6 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
|
|||
intel_can_enable_sagv(dev_priv, new_bw_state);
|
||||
}
|
||||
|
||||
if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
|
||||
intel_can_enable_sagv(dev_priv, old_bw_state)) {
|
||||
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
|
||||
ret = intel_atomic_lock_global_state(&new_bw_state->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ config DRM_IMX_DCSS
|
|||
tristate "i.MX8MQ DCSS"
|
||||
select IMX_IRQSTEER
|
||||
select DRM_KMS_HELPER
|
||||
select DRM_GEM_CMA_HELPER
|
||||
select VIDEOMODE_HELPERS
|
||||
depends on DRM && ARCH_MXC && ARM64
|
||||
help
|
||||
|
|
|
|||
|
|
@ -470,8 +470,8 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
|
|||
int32_t *msg, msg_type, handle;
|
||||
unsigned img_size = 0;
|
||||
void *ptr;
|
||||
|
||||
int i, r;
|
||||
long r;
|
||||
int i;
|
||||
|
||||
if (offset & 0x3F) {
|
||||
DRM_ERROR("UVD messages must be 64 byte aligned!\n");
|
||||
|
|
@ -481,13 +481,13 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
|
|||
r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false,
|
||||
MAX_SCHEDULE_TIMEOUT);
|
||||
if (r <= 0) {
|
||||
DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
|
||||
DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
|
||||
return r ? r : -ETIME;
|
||||
}
|
||||
|
||||
r = radeon_bo_kmap(bo, &ptr);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
|
||||
DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ config DRM_TEGRA
|
|||
depends on COMMON_CLK
|
||||
depends on DRM
|
||||
depends on OF
|
||||
select DRM_DP_AUX_BUS
|
||||
select DRM_KMS_HELPER
|
||||
select DRM_MIPI_DSI
|
||||
select DRM_PANEL
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/workqueue.h>
|
||||
|
||||
#include <drm/drm_dp_helper.h>
|
||||
#include <drm/drm_dp_aux_bus.h>
|
||||
#include <drm/drm_panel.h>
|
||||
|
||||
#include "dp.h"
|
||||
|
|
@ -570,6 +571,12 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
|
|||
list_add_tail(&dpaux->list, &dpaux_list);
|
||||
mutex_unlock(&dpaux_lock);
|
||||
|
||||
err = devm_of_dp_aux_populate_ep_devices(&dpaux->aux);
|
||||
if (err < 0) {
|
||||
dev_err(dpaux->dev, "failed to populate AUX bus: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ static void falcon_copy_firmware_image(struct falcon *falcon,
|
|||
|
||||
/* copy the whole thing taking into account endianness */
|
||||
for (i = 0; i < firmware->size / sizeof(u32); i++)
|
||||
virt[i] = le32_to_cpu(((u32 *)firmware->data)[i]);
|
||||
virt[i] = le32_to_cpu(((__le32 *)firmware->data)[i]);
|
||||
}
|
||||
|
||||
static int falcon_parse_firmware_image(struct falcon *falcon)
|
||||
|
|
|
|||
|
|
@ -525,9 +525,11 @@ int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
/*
|
||||
* post_crtc_powerdown will have called pm_runtime_put, so we
|
||||
* don't need it here otherwise we'll get the reference counting
|
||||
* wrong.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1749,6 +1749,7 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
|
|||
dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
|
||||
return PTR_ERR(codec_pdev);
|
||||
}
|
||||
vc4_hdmi->audio.codec_pdev = codec_pdev;
|
||||
|
||||
dai_link->cpus = &vc4_hdmi->audio.cpu;
|
||||
dai_link->codecs = &vc4_hdmi->audio.codec;
|
||||
|
|
@ -1788,6 +1789,12 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
|
|||
|
||||
}
|
||||
|
||||
static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
|
||||
{
|
||||
platform_device_unregister(vc4_hdmi->audio.codec_pdev);
|
||||
vc4_hdmi->audio.codec_pdev = NULL;
|
||||
}
|
||||
|
||||
static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
|
||||
{
|
||||
struct vc4_hdmi *vc4_hdmi = priv;
|
||||
|
|
@ -2660,6 +2667,7 @@ static void vc4_hdmi_unbind(struct device *dev, struct device *master,
|
|||
kfree(vc4_hdmi->hdmi_regset.regs);
|
||||
kfree(vc4_hdmi->hd_regset.regs);
|
||||
|
||||
vc4_hdmi_audio_exit(vc4_hdmi);
|
||||
vc4_hdmi_cec_exit(vc4_hdmi);
|
||||
vc4_hdmi_hotplug_exit(vc4_hdmi);
|
||||
vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
|
||||
|
|
|
|||
|
|
@ -116,6 +116,7 @@ struct vc4_hdmi_audio {
|
|||
struct snd_soc_dai_link_component platform;
|
||||
struct snd_dmaengine_dai_dma_data dma_data;
|
||||
struct hdmi_audio_infoframe infoframe;
|
||||
struct platform_device *codec_pdev;
|
||||
bool streaming;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -137,8 +137,15 @@ void host1x_syncpt_restore(struct host1x *host)
|
|||
struct host1x_syncpt *sp_base = host->syncpt;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < host1x_syncpt_nb_pts(host); i++)
|
||||
for (i = 0; i < host1x_syncpt_nb_pts(host); i++) {
|
||||
/*
|
||||
* Unassign syncpt from channels for purposes of Tegra186
|
||||
* syncpoint protection. This prevents any channel from
|
||||
* accessing it until it is reassigned.
|
||||
*/
|
||||
host1x_hw_syncpt_assign_to_channel(host, sp_base + i, NULL);
|
||||
host1x_hw_syncpt_restore(host, sp_base + i);
|
||||
}
|
||||
|
||||
for (i = 0; i < host1x_syncpt_nb_bases(host); i++)
|
||||
host1x_hw_syncpt_restore_wait_base(host, sp_base + i);
|
||||
|
|
@ -227,27 +234,12 @@ int host1x_syncpt_wait(struct host1x_syncpt *sp, u32 thresh, long timeout,
|
|||
void *ref;
|
||||
struct host1x_waitlist *waiter;
|
||||
int err = 0, check_count = 0;
|
||||
u32 val;
|
||||
|
||||
if (value)
|
||||
*value = 0;
|
||||
|
||||
/* first check cache */
|
||||
if (host1x_syncpt_is_expired(sp, thresh)) {
|
||||
if (value)
|
||||
*value = host1x_syncpt_load(sp);
|
||||
*value = host1x_syncpt_load(sp);
|
||||
|
||||
if (host1x_syncpt_is_expired(sp, thresh))
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* try to read from register */
|
||||
val = host1x_hw_syncpt_load(sp->host, sp);
|
||||
if (host1x_syncpt_is_expired(sp, thresh)) {
|
||||
if (value)
|
||||
*value = val;
|
||||
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (!timeout) {
|
||||
err = -EAGAIN;
|
||||
|
|
@ -352,13 +344,6 @@ int host1x_syncpt_init(struct host1x *host)
|
|||
for (i = 0; i < host->info->nb_pts; i++) {
|
||||
syncpt[i].id = i;
|
||||
syncpt[i].host = host;
|
||||
|
||||
/*
|
||||
* Unassign syncpt from channels for purposes of Tegra186
|
||||
* syncpoint protection. This prevents any channel from
|
||||
* accessing it until it is reassigned.
|
||||
*/
|
||||
host1x_hw_syncpt_assign_to_channel(host, &syncpt[i], NULL);
|
||||
}
|
||||
|
||||
for (i = 0; i < host->info->nb_bases; i++)
|
||||
|
|
|
|||
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