ASoC: cs35l41: Correct handling of some registers in the cache
It makes no sense to cache the test/user key registers, since they require values written at specific times, mark them volatile. It is probably best if they can't be accessed from user-space either, so mark them precious as well. The interrupt force, edge, polarity and debounce are all settings applied to the IRQ rather than status bits and as such should not be volatile. The OTP trim values will require re-application in the event of a cache sync and as such should not be volatile. The OTPID however should be volatile. The DSP scratch registers are used to read back an error/debug code from the DSP on shutdown, as such these should be marked volatile. Finally, add some missing defaults, add TST_FS_MON0, and allow the DSP core control register to be cached. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20220105113026.18955-5-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Charles Keepax
Mark Brown
Родитель
56852cf4b2
Коммит
5f2f539901
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@ -20,6 +20,11 @@ static const struct reg_default cs35l41_reg[] = {
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{ CS35L41_PWR_CTRL2, 0x00000000 },
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{ CS35L41_PWR_CTRL3, 0x01000010 },
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{ CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
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{ CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
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{ CS35L41_TST_FS_MON0, 0x00020016 },
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{ CS35L41_BSTCVRT_COEFF, 0x00002424 },
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{ CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
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{ CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
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{ CS35L41_SP_ENABLES, 0x00000000 },
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{ CS35L41_SP_RATE_CTRL, 0x00000028 },
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{ CS35L41_SP_FORMAT, 0x18180200 },
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@ -48,11 +53,16 @@ static const struct reg_default cs35l41_reg[] = {
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{ CS35L41_WKFET_CFG, 0x00000111 },
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{ CS35L41_NG_CFG, 0x00000033 },
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{ CS35L41_AMP_GAIN_CTRL, 0x00000000 },
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{ CS35L41_IRQ1_MASK1, 0xFFFFFFFF },
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{ CS35L41_IRQ1_MASK2, 0xFFFFFFFF },
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{ CS35L41_IRQ1_MASK3, 0xFFFF87FF },
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{ CS35L41_IRQ1_MASK4, 0xFEFFFFFF },
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{ CS35L41_GPIO1_CTRL1, 0xE1000001 },
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{ CS35L41_GPIO2_CTRL1, 0xE1000001 },
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{ CS35L41_MIXER_NGATE_CFG, 0x00000000 },
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{ CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
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{ CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
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{ CS35L41_DSP1_CCM_CORE_CTRL, 0x00000101 },
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};
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static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
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@ -84,6 +94,7 @@ static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
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case CS35L41_DSP_CLK_CTRL:
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case CS35L41_GLOBAL_CLK_CTRL:
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case CS35L41_DATA_FS_SEL:
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case CS35L41_TST_FS_MON0:
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case CS35L41_MDSYNC_EN:
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case CS35L41_MDSYNC_TX_ID:
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case CS35L41_MDSYNC_PWR_CTRL:
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@ -342,7 +353,10 @@ static bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
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static bool cs35l41_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CS35L41_TEST_KEY_CTL:
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case CS35L41_USER_KEY_CTL:
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case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
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case CS35L41_TST_FS_MON0:
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case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
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case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532:
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case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
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@ -359,6 +373,9 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
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case CS35L41_SFT_RESET:
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case CS35L41_FABID:
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case CS35L41_REVID:
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case CS35L41_OTPID:
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case CS35L41_TEST_KEY_CTL:
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case CS35L41_USER_KEY_CTL:
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case CS35L41_DTEMP_EN:
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case CS35L41_IRQ1_STATUS:
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case CS35L41_IRQ1_STATUS1:
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@ -369,17 +386,6 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
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case CS35L41_IRQ1_RAW_STATUS2:
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case CS35L41_IRQ1_RAW_STATUS3:
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case CS35L41_IRQ1_RAW_STATUS4:
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case CS35L41_IRQ1_FRC1:
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case CS35L41_IRQ1_FRC2:
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case CS35L41_IRQ1_FRC3:
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case CS35L41_IRQ1_FRC4:
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case CS35L41_IRQ1_EDGE1:
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case CS35L41_IRQ1_EDGE4:
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case CS35L41_IRQ1_POL1:
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case CS35L41_IRQ1_POL2:
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case CS35L41_IRQ1_POL3:
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case CS35L41_IRQ1_POL4:
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case CS35L41_IRQ1_DB3:
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case CS35L41_IRQ2_STATUS:
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case CS35L41_IRQ2_STATUS1:
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case CS35L41_IRQ2_STATUS2:
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@ -389,54 +395,7 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
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case CS35L41_IRQ2_RAW_STATUS2:
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case CS35L41_IRQ2_RAW_STATUS3:
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case CS35L41_IRQ2_RAW_STATUS4:
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case CS35L41_IRQ2_FRC1:
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case CS35L41_IRQ2_FRC2:
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case CS35L41_IRQ2_FRC3:
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case CS35L41_IRQ2_FRC4:
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case CS35L41_IRQ2_EDGE1:
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case CS35L41_IRQ2_EDGE4:
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case CS35L41_IRQ2_POL1:
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case CS35L41_IRQ2_POL2:
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case CS35L41_IRQ2_POL3:
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case CS35L41_IRQ2_POL4:
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case CS35L41_IRQ2_DB3:
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case CS35L41_GPIO_STATUS1:
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case CS35L41_OTP_TRIM_1:
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case CS35L41_OTP_TRIM_2:
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case CS35L41_OTP_TRIM_3:
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case CS35L41_OTP_TRIM_4:
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case CS35L41_OTP_TRIM_5:
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case CS35L41_OTP_TRIM_6:
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case CS35L41_OTP_TRIM_7:
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case CS35L41_OTP_TRIM_8:
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case CS35L41_OTP_TRIM_9:
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case CS35L41_OTP_TRIM_10:
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case CS35L41_OTP_TRIM_11:
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case CS35L41_OTP_TRIM_12:
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case CS35L41_OTP_TRIM_13:
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case CS35L41_OTP_TRIM_14:
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case CS35L41_OTP_TRIM_15:
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case CS35L41_OTP_TRIM_16:
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case CS35L41_OTP_TRIM_17:
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case CS35L41_OTP_TRIM_18:
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case CS35L41_OTP_TRIM_19:
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case CS35L41_OTP_TRIM_20:
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case CS35L41_OTP_TRIM_21:
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case CS35L41_OTP_TRIM_22:
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case CS35L41_OTP_TRIM_23:
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case CS35L41_OTP_TRIM_24:
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case CS35L41_OTP_TRIM_25:
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case CS35L41_OTP_TRIM_26:
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case CS35L41_OTP_TRIM_27:
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case CS35L41_OTP_TRIM_28:
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case CS35L41_OTP_TRIM_29:
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case CS35L41_OTP_TRIM_30:
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case CS35L41_OTP_TRIM_31:
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case CS35L41_OTP_TRIM_32:
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case CS35L41_OTP_TRIM_33:
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case CS35L41_OTP_TRIM_34:
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case CS35L41_OTP_TRIM_35:
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case CS35L41_OTP_TRIM_36:
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case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8:
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case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068:
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case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046:
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@ -445,7 +404,11 @@ static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
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case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022:
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case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045:
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case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114:
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case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS:
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case CS35L41_DSP1_SCRATCH1:
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case CS35L41_DSP1_SCRATCH2:
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case CS35L41_DSP1_SCRATCH3:
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case CS35L41_DSP1_SCRATCH4:
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case CS35L41_DSP1_CCM_CLK_OVERRIDE ... CS35L41_DSP1_WDT_STATUS:
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case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31:
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return true;
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default:
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