serial: samsung: switch to clkdev based clock lookup
Instead of using clock names supplied in platform data, use a generic clock name 'clk_uart_baud' to look up clocks. The platform code should register clocks with the name 'clk_uart_baud' which can be used by the baud rate generator. The clock lookup and selection of the best clock as baud rate clock is reworked. Platform code can specify the clocks that can be used as source for the baud clock (as supported previously by passing names of clocks). A new member is added to the platform data 'clk_sel' which holds a bit-field value with each bit representing a baud source clock. If a bit at any bit position is set, that clock is looked up to participate in the selection of the baud clock source. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Thomas Abraham
Kukjin Kim
Родитель
046c217c65
Коммит
5f5a7a5578
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@ -222,6 +222,10 @@
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#define S5PV210_UFSTAT_RXSHIFT (0)
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#define NO_NEED_CHECK_CLKSRC 1
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#define S3C2410_UCON_CLKSEL0 (1 << 0)
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#define S3C2410_UCON_CLKSEL1 (1 << 1)
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#define S3C2410_UCON_CLKSEL2 (1 << 2)
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#define S3C2410_UCON_CLKSEL3 (1 << 3)
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#ifndef __ASSEMBLY__
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@ -257,6 +261,7 @@ struct s3c2410_uartcfg {
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unsigned char unused;
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unsigned short flags;
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upf_t uart_flags; /* default uart flags */
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unsigned int clk_sel;
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unsigned int has_fracval;
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@ -49,6 +49,7 @@
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#include <mach/map.h>
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#include <plat/regs-serial.h>
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#include <plat/clock.h>
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#include "samsung.h"
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@ -558,133 +559,98 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
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*
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*/
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#define MAX_CLK_NAME_LENGTH 15
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#define MAX_CLKS (8)
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static struct s3c24xx_uart_clksrc tmp_clksrc = {
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.name = "pclk",
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.min_baud = 0,
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.max_baud = 0,
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.divisor = 1,
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};
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static inline int
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s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
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static inline int s3c24xx_serial_getsource(struct uart_port *port)
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{
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struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
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unsigned int ucon;
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return (info->get_clksrc)(port, c);
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}
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static inline int
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s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
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{
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struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
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return (info->set_clksrc)(port, c);
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}
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struct baud_calc {
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struct s3c24xx_uart_clksrc *clksrc;
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unsigned int calc;
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unsigned int divslot;
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unsigned int quot;
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struct clk *src;
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};
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static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
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struct uart_port *port,
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struct s3c24xx_uart_clksrc *clksrc,
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unsigned int baud)
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{
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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unsigned long rate;
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calc->src = clk_get(port->dev, clksrc->name);
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if (calc->src == NULL || IS_ERR(calc->src))
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if (info->num_clks == 1)
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return 0;
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rate = clk_get_rate(calc->src);
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rate /= clksrc->divisor;
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calc->clksrc = clksrc;
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if (ourport->info->has_divslot) {
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unsigned long div = rate / baud;
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/* The UDIVSLOT register on the newer UARTs allows us to
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* get a divisor adjustment of 1/16th on the baud clock.
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*
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* We don't keep the UDIVSLOT value (the 16ths we calculated
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* by not multiplying the baud by 16) as it is easy enough
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* to recalculate.
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*/
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calc->quot = div / 16;
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calc->calc = rate / div;
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} else {
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calc->quot = (rate + (8 * baud)) / (16 * baud);
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calc->calc = (rate / (calc->quot * 16));
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}
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calc->quot--;
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return 1;
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ucon = rd_regl(port, S3C2410_UCON);
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ucon &= info->clksel_mask;
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return ucon >> info->clksel_shift;
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}
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static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
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struct s3c24xx_uart_clksrc **clksrc,
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struct clk **clk,
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unsigned int baud)
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static void s3c24xx_serial_setsource(struct uart_port *port,
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unsigned int clk_sel)
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{
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struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
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struct s3c24xx_uart_clksrc *clkp;
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struct baud_calc res[MAX_CLKS];
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struct baud_calc *resptr, *best, *sptr;
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int i;
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struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
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unsigned int ucon;
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clkp = cfg->clocks;
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best = NULL;
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if (info->num_clks == 1)
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return;
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if (cfg->clocks_size < 2) {
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if (cfg->clocks_size == 0)
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clkp = &tmp_clksrc;
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ucon = rd_regl(port, S3C2410_UCON);
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if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
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return;
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s3c24xx_serial_calcbaud(res, port, clkp, baud);
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best = res;
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resptr = best + 1;
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} else {
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resptr = res;
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ucon &= ~info->clksel_mask;
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ucon |= clk_sel << info->clksel_shift;
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wr_regl(port, S3C2410_UCON, ucon);
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}
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for (i = 0; i < cfg->clocks_size; i++, clkp++) {
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if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
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resptr++;
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static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
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unsigned int req_baud, struct clk **best_clk,
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unsigned int *clk_num)
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{
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struct s3c24xx_uart_info *info = ourport->info;
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struct clk *clk;
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unsigned long rate;
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unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
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char clkname[MAX_CLK_NAME_LENGTH];
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int calc_deviation, deviation = (1 << 30) - 1;
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*best_clk = NULL;
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clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
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ourport->info->def_clk_sel;
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for (cnt = 0; cnt < info->num_clks; cnt++) {
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if (!(clk_sel & (1 << cnt)))
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continue;
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sprintf(clkname, "clk_uart_baud%d", cnt);
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clk = clk_get(ourport->port.dev, clkname);
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if (IS_ERR_OR_NULL(clk))
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continue;
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rate = clk_get_rate(clk);
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if (!rate)
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continue;
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if (ourport->info->has_divslot) {
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unsigned long div = rate / req_baud;
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/* The UDIVSLOT register on the newer UARTs allows us to
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* get a divisor adjustment of 1/16th on the baud clock.
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*
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* We don't keep the UDIVSLOT value (the 16ths we
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* calculated by not multiplying the baud by 16) as it
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* is easy enough to recalculate.
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*/
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quot = div / 16;
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baud = rate / div;
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} else {
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quot = (rate + (8 * req_baud)) / (16 * req_baud);
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baud = rate / (quot * 16);
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}
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quot--;
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calc_deviation = req_baud - baud;
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if (calc_deviation < 0)
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calc_deviation = -calc_deviation;
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if (calc_deviation < deviation) {
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*best_clk = clk;
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best_quot = quot;
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*clk_num = cnt;
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deviation = calc_deviation;
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}
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}
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/* ok, we now need to select the best clock we found */
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if (!best) {
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unsigned int deviation = (1<<30)|((1<<30)-1);
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int calc_deviation;
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for (sptr = res; sptr < resptr; sptr++) {
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calc_deviation = baud - sptr->calc;
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if (calc_deviation < 0)
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calc_deviation = -calc_deviation;
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if (calc_deviation < deviation) {
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best = sptr;
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deviation = calc_deviation;
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}
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}
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}
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/* store results to pass back */
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*clksrc = best->clksrc;
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*clk = best->src;
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return best->quot;
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return best_quot;
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}
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/* udivslot_table[]
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@ -717,10 +683,9 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
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{
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struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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struct s3c24xx_uart_clksrc *clksrc = NULL;
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struct clk *clk = NULL;
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unsigned long flags;
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unsigned int baud, quot;
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unsigned int baud, quot, clk_sel = 0;
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unsigned int ulcon;
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unsigned int umcon;
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unsigned int udivslot = 0;
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@ -736,17 +701,16 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
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*/
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baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
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quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
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if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
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quot = port->custom_divisor;
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else
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quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
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if (!clk)
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return;
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/* check to see if we need to change clock source */
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if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
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dbg("selecting clock %p\n", clk);
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s3c24xx_serial_setsource(port, clksrc);
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if (ourport->baudclk != clk) {
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s3c24xx_serial_setsource(port, clk_sel);
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if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
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clk_disable(ourport->baudclk);
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@ -755,7 +719,6 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
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clk_enable(clk);
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ourport->clksrc = clksrc;
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ourport->baudclk = clk;
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ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
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}
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@ -1202,7 +1165,7 @@ static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
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struct uart_port *port = s3c24xx_dev_to_port(dev);
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
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return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->baudclk->name);
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}
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static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
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@ -1382,12 +1345,13 @@ static void __init
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s3c24xx_serial_get_options(struct uart_port *port, int *baud,
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int *parity, int *bits)
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{
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struct s3c24xx_uart_clksrc clksrc;
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struct clk *clk;
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unsigned int ulcon;
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unsigned int ucon;
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unsigned int ubrdiv;
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unsigned long rate;
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unsigned int clk_sel;
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char clk_name[MAX_CLK_NAME_LENGTH];
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ulcon = rd_regl(port, S3C2410_ULCON);
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ucon = rd_regl(port, S3C2410_UCON);
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@ -1432,11 +1396,12 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud,
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/* now calculate the baud rate */
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s3c24xx_serial_getsource(port, &clksrc);
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clk_sel = s3c24xx_serial_getsource(port);
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sprintf(clk_name, "clk_uart_baud%d", clk_sel);
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clk = clk_get(port->dev, clksrc.name);
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clk = clk_get(port->dev, clk_name);
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if (!IS_ERR(clk) && clk != NULL)
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rate = clk_get_rate(clk) / clksrc.divisor;
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rate = clk_get_rate(clk);
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else
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rate = 1;
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@ -19,6 +19,10 @@ struct s3c24xx_uart_info {
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unsigned long tx_fifomask;
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unsigned long tx_fifoshift;
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unsigned long tx_fifofull;
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unsigned int def_clk_sel;
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unsigned long num_clks;
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unsigned long clksel_mask;
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unsigned long clksel_shift;
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/* uart port features */
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