PCI: xgene: Add APM X-Gene PCIe driver
Add the AppliedMicro X-Gene SOC PCIe host controller driver. The X-Gene PCIe controller supports up to 8 lanes and GEN3 speed. The X-Gene SOC supports up to 5 PCIe ports. [bhelgaas: folded in MAINTAINERS and bindings updates] Tested-by: Ming Lei <ming.lei@canonical.com> Tested-by: Dann Frazier <dann.frazier@canonical.com> Signed-off-by: Tanmay Inamdar <tinamdar@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)
This commit is contained in:
Tanmay Inamdar
Bjorn Helgaas
Родитель
d1e6dc91b5
Коммит
5f6b6ccdbe
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@ -0,0 +1,57 @@
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* AppliedMicro X-Gene PCIe interface
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Required properties:
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- device_type: set to "pci"
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- compatible: should contain "apm,xgene-pcie" to identify the core.
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names
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property.
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- reg-names: Must include the following entries:
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"csr": controller configuration registers.
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"cfg": pcie configuration space registers.
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- ranges: ranges for the outbound memory, I/O regions.
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- dma-ranges: ranges for the inbound memory regions.
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- clocks: from common clock binding: handle to pci clock.
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Optional properties:
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- status: Either "ok" or "disabled".
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- dma-coherent: Present if dma operations are coherent
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Example:
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SoC specific DT Entry:
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pcie0: pcie@1f2b0000 {
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status = "disabled";
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device_type = "pci";
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compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
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0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
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reg-names = "csr", "cfg";
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ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
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0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
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0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
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0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
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0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
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0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
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dma-coherent;
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clocks = <&pcie0clk 0>;
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};
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Board specific DT Entry:
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&pcie0 {
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status = "ok";
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};
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@ -6868,6 +6868,14 @@ F: include/linux/pci*
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F: arch/x86/pci/
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F: arch/x86/kernel/quirks.c
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PCI DRIVER FOR APPLIEDMICRO XGENE
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M: Tanmay Inamdar <tinamdar@apm.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/xgene-pci.txt
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F: drivers/pci/host/pci-xgene.c
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PCI DRIVER FOR IMX6
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M: Richard Zhu <r65037@freescale.com>
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M: Shawn Guo <shawn.guo@freescale.com>
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@ -63,4 +63,14 @@ config PCIE_SPEAR13XX
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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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config PCI_XGENE
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bool "X-Gene PCIe controller"
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depends on ARCH_XGENE
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depends on OF
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select PCIEPORTBUS
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help
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Say Y here if you want internal PCI support on APM X-Gene SoC.
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There are 5 internal PCIe ports available. Each port is GEN3 capable
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and have varied lanes from x1 to x8.
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endmenu
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@ -8,3 +8,4 @@ obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
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obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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@ -0,0 +1,659 @@
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/**
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* APM X-Gene PCIe Driver
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*
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* Copyright (c) 2014 Applied Micro Circuits Corporation.
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*
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* Author: Tanmay Inamdar <tinamdar@apm.com>.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clk-private.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/memblock.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define PCIECORE_CTLANDSTATUS 0x50
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#define PIM1_1L 0x80
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#define IBAR2 0x98
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#define IR2MSK 0x9c
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#define PIM2_1L 0xa0
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#define IBAR3L 0xb4
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#define IR3MSKL 0xbc
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#define PIM3_1L 0xc4
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#define OMR1BARL 0x100
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#define OMR2BARL 0x118
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#define OMR3BARL 0x130
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#define CFGBARL 0x154
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#define CFGBARH 0x158
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#define CFGCTL 0x15c
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#define RTDID 0x160
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#define BRIDGE_CFG_0 0x2000
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#define BRIDGE_CFG_4 0x2010
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#define BRIDGE_STATUS_0 0x2600
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#define LINK_UP_MASK 0x00000100
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#define AXI_EP_CFG_ACCESS 0x10000
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#define EN_COHERENCY 0xF0000000
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#define EN_REG 0x00000001
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#define OB_LO_IO 0x00000002
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#define XGENE_PCIE_VENDORID 0x10E8
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#define XGENE_PCIE_DEVICEID 0xE004
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#define SZ_1T (SZ_1G*1024ULL)
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#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
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struct xgene_pcie_port {
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struct device_node *node;
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struct device *dev;
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struct clk *clk;
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void __iomem *csr_base;
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void __iomem *cfg_base;
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unsigned long cfg_addr;
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bool link_up;
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};
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static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
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{
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return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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}
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/* PCIe Configuration Out/In */
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static inline void xgene_pcie_cfg_out32(void __iomem *addr, int offset, u32 val)
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{
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writel(val, addr + offset);
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}
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static inline void xgene_pcie_cfg_out16(void __iomem *addr, int offset, u16 val)
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{
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u32 val32 = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 2:
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val32 &= ~0xFFFF0000;
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val32 |= (u32)val << 16;
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break;
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case 0:
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default:
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val32 &= ~0xFFFF;
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val32 |= val;
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break;
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}
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writel(val32, addr + (offset & ~0x3));
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}
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static inline void xgene_pcie_cfg_out8(void __iomem *addr, int offset, u8 val)
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{
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u32 val32 = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 0:
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val32 &= ~0xFF;
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val32 |= val;
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break;
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case 1:
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val32 &= ~0xFF00;
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val32 |= (u32)val << 8;
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break;
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case 2:
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val32 &= ~0xFF0000;
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val32 |= (u32)val << 16;
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break;
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case 3:
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default:
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val32 &= ~0xFF000000;
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val32 |= (u32)val << 24;
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break;
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}
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writel(val32, addr + (offset & ~0x3));
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}
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static inline void xgene_pcie_cfg_in32(void __iomem *addr, int offset, u32 *val)
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{
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*val = readl(addr + offset);
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}
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static inline void xgene_pcie_cfg_in16(void __iomem *addr, int offset, u32 *val)
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{
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*val = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 2:
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*val >>= 16;
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break;
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}
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*val &= 0xFFFF;
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}
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static inline void xgene_pcie_cfg_in8(void __iomem *addr, int offset, u32 *val)
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{
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*val = readl(addr + (offset & ~0x3));
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switch (offset & 0x3) {
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case 3:
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*val = *val >> 24;
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break;
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case 2:
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*val = *val >> 16;
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break;
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case 1:
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*val = *val >> 8;
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break;
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}
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*val &= 0xFF;
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}
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/*
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* When the address bit [17:16] is 2'b01, the Configuration access will be
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* treated as Type 1 and it will be forwarded to external PCIe device.
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*/
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static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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if (bus->number >= (bus->primary + 1))
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return port->cfg_base + AXI_EP_CFG_ACCESS;
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return port->cfg_base;
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}
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/*
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* For Configuration request, RTDID register is used as Bus Number,
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* Device Number and Function number of the header fields.
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*/
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static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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unsigned int b, d, f;
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u32 rtdid_val = 0;
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b = bus->number;
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d = PCI_SLOT(devfn);
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f = PCI_FUNC(devfn);
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if (!pci_is_root_bus(bus))
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rtdid_val = (b << 8) | (d << 3) | f;
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writel(rtdid_val, port->csr_base + RTDID);
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/* read the register back to ensure flush */
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readl(port->csr_base + RTDID);
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}
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/*
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* X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
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* the translation from PCI bus to native BUS. Entire DDR region
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* is mapped into PCIe space using these registers, so it can be
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* reached by DMA from EP devices. The BAR0/1 of bridge should be
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* hidden during enumeration to avoid the sizing and resource allocation
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* by PCIe core.
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*/
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static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
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{
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if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
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(offset == PCI_BASE_ADDRESS_1)))
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return true;
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return false;
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}
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static int xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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void __iomem *addr;
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if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (xgene_pcie_hide_rc_bars(bus, offset)) {
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*val = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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xgene_pcie_set_rtdid_reg(bus, devfn);
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addr = xgene_pcie_get_cfg_base(bus);
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switch (len) {
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case 1:
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xgene_pcie_cfg_in8(addr, offset, val);
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break;
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case 2:
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xgene_pcie_cfg_in16(addr, offset, val);
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break;
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default:
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xgene_pcie_cfg_in32(addr, offset, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int xgene_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct xgene_pcie_port *port = bus->sysdata;
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void __iomem *addr;
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if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (xgene_pcie_hide_rc_bars(bus, offset))
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return PCIBIOS_SUCCESSFUL;
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xgene_pcie_set_rtdid_reg(bus, devfn);
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addr = xgene_pcie_get_cfg_base(bus);
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switch (len) {
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case 1:
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xgene_pcie_cfg_out8(addr, offset, (u8)val);
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break;
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case 2:
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xgene_pcie_cfg_out16(addr, offset, (u16)val);
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break;
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default:
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xgene_pcie_cfg_out32(addr, offset, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops xgene_pcie_ops = {
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.read = xgene_pcie_read_config,
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.write = xgene_pcie_write_config
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};
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static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
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u32 flags, u64 size)
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{
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u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
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u32 val32 = 0;
|
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u32 val;
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val32 = readl(csr_base + addr);
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val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
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writel(val, csr_base + addr);
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val32 = readl(csr_base + addr + 0x04);
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val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
|
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writel(val, csr_base + addr + 0x04);
|
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||||
val32 = readl(csr_base + addr + 0x04);
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||||
val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
|
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writel(val, csr_base + addr + 0x04);
|
||||
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val32 = readl(csr_base + addr + 0x08);
|
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val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
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writel(val, csr_base + addr + 0x08);
|
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|
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return mask;
|
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}
|
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|
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static void xgene_pcie_linkup(struct xgene_pcie_port *port,
|
||||
u32 *lanes, u32 *speed)
|
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{
|
||||
void __iomem *csr_base = port->csr_base;
|
||||
u32 val32;
|
||||
|
||||
port->link_up = false;
|
||||
val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
|
||||
if (val32 & LINK_UP_MASK) {
|
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port->link_up = true;
|
||||
*speed = PIPE_PHY_RATE_RD(val32);
|
||||
val32 = readl(csr_base + BRIDGE_STATUS_0);
|
||||
*lanes = val32 >> 26;
|
||||
}
|
||||
}
|
||||
|
||||
static int xgene_pcie_init_port(struct xgene_pcie_port *port)
|
||||
{
|
||||
int rc;
|
||||
|
||||
port->clk = clk_get(port->dev, NULL);
|
||||
if (IS_ERR(port->clk)) {
|
||||
dev_err(port->dev, "clock not available\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
rc = clk_prepare_enable(port->clk);
|
||||
if (rc) {
|
||||
dev_err(port->dev, "clock enable failed\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
|
||||
port->csr_base = devm_ioremap_resource(port->dev, res);
|
||||
if (IS_ERR(port->csr_base))
|
||||
return PTR_ERR(port->csr_base);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
|
||||
port->cfg_base = devm_ioremap_resource(port->dev, res);
|
||||
if (IS_ERR(port->cfg_base))
|
||||
return PTR_ERR(port->cfg_base);
|
||||
port->cfg_addr = res->start;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
|
||||
struct resource *res, u32 offset,
|
||||
u64 cpu_addr, u64 pci_addr)
|
||||
{
|
||||
void __iomem *base = port->csr_base + offset;
|
||||
resource_size_t size = resource_size(res);
|
||||
u64 restype = resource_type(res);
|
||||
u64 mask = 0;
|
||||
u32 min_size;
|
||||
u32 flag = EN_REG;
|
||||
|
||||
if (restype == IORESOURCE_MEM) {
|
||||
min_size = SZ_128M;
|
||||
} else {
|
||||
min_size = 128;
|
||||
flag |= OB_LO_IO;
|
||||
}
|
||||
|
||||
if (size >= min_size)
|
||||
mask = ~(size - 1) | flag;
|
||||
else
|
||||
dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n",
|
||||
(u64)size, min_size);
|
||||
|
||||
writel(lower_32_bits(cpu_addr), base);
|
||||
writel(upper_32_bits(cpu_addr), base + 0x04);
|
||||
writel(lower_32_bits(mask), base + 0x08);
|
||||
writel(upper_32_bits(mask), base + 0x0c);
|
||||
writel(lower_32_bits(pci_addr), base + 0x10);
|
||||
writel(upper_32_bits(pci_addr), base + 0x14);
|
||||
}
|
||||
|
||||
static void xgene_pcie_setup_cfg_reg(void __iomem *csr_base, u64 addr)
|
||||
{
|
||||
writel(lower_32_bits(addr), csr_base + CFGBARL);
|
||||
writel(upper_32_bits(addr), csr_base + CFGBARH);
|
||||
writel(EN_REG, csr_base + CFGCTL);
|
||||
}
|
||||
|
||||
static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
|
||||
struct list_head *res,
|
||||
resource_size_t io_base)
|
||||
{
|
||||
struct pci_host_bridge_window *window;
|
||||
struct device *dev = port->dev;
|
||||
int ret;
|
||||
|
||||
list_for_each_entry(window, res, list) {
|
||||
struct resource *res = window->res;
|
||||
u64 restype = resource_type(res);
|
||||
|
||||
dev_dbg(port->dev, "%pR\n", res);
|
||||
|
||||
switch (restype) {
|
||||
case IORESOURCE_IO:
|
||||
xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
|
||||
res->start - window->offset);
|
||||
ret = pci_remap_iospace(res, io_base);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
break;
|
||||
case IORESOURCE_MEM:
|
||||
xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start,
|
||||
res->start - window->offset);
|
||||
break;
|
||||
case IORESOURCE_BUS:
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "invalid resource %pR\n", res);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void xgene_pcie_setup_pims(void *addr, u64 pim, u64 size)
|
||||
{
|
||||
writel(lower_32_bits(pim), addr);
|
||||
writel(upper_32_bits(pim) | EN_COHERENCY, addr + 0x04);
|
||||
writel(lower_32_bits(size), addr + 0x10);
|
||||
writel(upper_32_bits(size), addr + 0x14);
|
||||
}
|
||||
|
||||
/*
|
||||
* X-Gene PCIe support maximum 3 inbound memory regions
|
||||
* This function helps to select a region based on size of region
|
||||
*/
|
||||
static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
|
||||
{
|
||||
if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
|
||||
*ib_reg_mask |= (1 << 1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
|
||||
*ib_reg_mask |= (1 << 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
|
||||
*ib_reg_mask |= (1 << 2);
|
||||
return 2;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
|
||||
struct of_pci_range *range, u8 *ib_reg_mask)
|
||||
{
|
||||
void __iomem *csr_base = port->csr_base;
|
||||
void __iomem *cfg_base = port->cfg_base;
|
||||
void *bar_addr;
|
||||
void *pim_addr;
|
||||
u64 cpu_addr = range->cpu_addr;
|
||||
u64 pci_addr = range->pci_addr;
|
||||
u64 size = range->size;
|
||||
u64 mask = ~(size - 1) | EN_REG;
|
||||
u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
|
||||
u32 bar_low;
|
||||
int region;
|
||||
|
||||
region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
|
||||
if (region < 0) {
|
||||
dev_warn(port->dev, "invalid pcie dma-range config\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (range->flags & IORESOURCE_PREFETCH)
|
||||
flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
|
||||
|
||||
bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
|
||||
switch (region) {
|
||||
case 0:
|
||||
xgene_pcie_set_ib_mask(csr_base, BRIDGE_CFG_4, flags, size);
|
||||
bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
|
||||
writel(bar_low, bar_addr);
|
||||
writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
|
||||
pim_addr = csr_base + PIM1_1L;
|
||||
break;
|
||||
case 1:
|
||||
bar_addr = csr_base + IBAR2;
|
||||
writel(bar_low, bar_addr);
|
||||
writel(lower_32_bits(mask), csr_base + IR2MSK);
|
||||
pim_addr = csr_base + PIM2_1L;
|
||||
break;
|
||||
case 2:
|
||||
bar_addr = csr_base + IBAR3L;
|
||||
writel(bar_low, bar_addr);
|
||||
writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
|
||||
writel(lower_32_bits(mask), csr_base + IR3MSKL);
|
||||
writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
|
||||
pim_addr = csr_base + PIM3_1L;
|
||||
break;
|
||||
}
|
||||
|
||||
xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1));
|
||||
}
|
||||
|
||||
static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
|
||||
struct device_node *node)
|
||||
{
|
||||
const int na = 3, ns = 2;
|
||||
int rlen;
|
||||
|
||||
parser->node = node;
|
||||
parser->pna = of_n_addr_cells(node);
|
||||
parser->np = parser->pna + na + ns;
|
||||
|
||||
parser->range = of_get_property(node, "dma-ranges", &rlen);
|
||||
if (!parser->range)
|
||||
return -ENOENT;
|
||||
parser->end = parser->range + rlen / sizeof(__be32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
|
||||
{
|
||||
struct device_node *np = port->node;
|
||||
struct of_pci_range range;
|
||||
struct of_pci_range_parser parser;
|
||||
struct device *dev = port->dev;
|
||||
u8 ib_reg_mask = 0;
|
||||
|
||||
if (pci_dma_range_parser_init(&parser, np)) {
|
||||
dev_err(dev, "missing dma-ranges property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Get the dma-ranges from DT */
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
u64 end = range.cpu_addr + range.size - 1;
|
||||
|
||||
dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
|
||||
range.flags, range.cpu_addr, end, range.pci_addr);
|
||||
xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* clear BAR configuration which was done by firmware */
|
||||
static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = PIM1_1L; i <= CFGCTL; i += 4)
|
||||
writel(0x0, port->csr_base + i);
|
||||
}
|
||||
|
||||
static int xgene_pcie_setup(struct xgene_pcie_port *port,
|
||||
struct list_head *res,
|
||||
resource_size_t io_base)
|
||||
{
|
||||
u32 val, lanes = 0, speed = 0;
|
||||
int ret;
|
||||
|
||||
xgene_pcie_clear_config(port);
|
||||
|
||||
/* setup the vendor and device IDs correctly */
|
||||
val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
|
||||
writel(val, port->csr_base + BRIDGE_CFG_0);
|
||||
|
||||
ret = xgene_pcie_map_ranges(port, res, io_base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = xgene_pcie_parse_map_dma_ranges(port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
xgene_pcie_linkup(port, &lanes, &speed);
|
||||
if (!port->link_up)
|
||||
dev_info(port->dev, "(rc) link down\n");
|
||||
else
|
||||
dev_info(port->dev, "(rc) x%d gen-%d link up\n",
|
||||
lanes, speed + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xgene_pcie_probe_bridge(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *dn = pdev->dev.of_node;
|
||||
struct xgene_pcie_port *port;
|
||||
resource_size_t iobase = 0;
|
||||
struct pci_bus *bus;
|
||||
int ret;
|
||||
LIST_HEAD(res);
|
||||
|
||||
port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
port->node = of_node_get(pdev->dev.of_node);
|
||||
port->dev = &pdev->dev;
|
||||
|
||||
ret = xgene_pcie_map_reg(port, pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = xgene_pcie_init_port(port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = xgene_pcie_setup(port, &res, iobase);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
bus = pci_scan_root_bus(&pdev->dev, 0, &xgene_pcie_ops, port, &res);
|
||||
if (!bus)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, port);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id xgene_pcie_match_table[] = {
|
||||
{.compatible = "apm,xgene-pcie",},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver xgene_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "xgene-pcie",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(xgene_pcie_match_table),
|
||||
},
|
||||
.probe = xgene_pcie_probe_bridge,
|
||||
};
|
||||
module_platform_driver(xgene_pcie_driver);
|
||||
|
||||
MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>");
|
||||
MODULE_DESCRIPTION("APM X-Gene PCIe driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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