phy: qcom-qmp: pcs: Add v6.20 register offsets
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
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#define QCOM_PHY_QMP_PCS_V6_20_H_
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/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
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#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
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#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
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#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
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#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
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#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
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#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
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#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
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#endif
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#include "phy-qcom-qmp-pcs-v6.h"
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#include "phy-qcom-qmp-pcs-v6_20.h"
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/* Only for QMP V3 & V4 PHY - DP COM registers */
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#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
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#define QPHY_V3_DP_COM_SW_RESET 0x04
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