[POWERPC] Fixup error handling when emulating a floating point instruction
When we do full FP emulation its possible that we need to post a SIGFPE based on the results of the emulation. The previous code ignored this case completely. Additionally, the Soft_emulate_8xx case had two issues. One, we should never generate a SIGFPE since the code only does data movement. Second, we were interpreting the return codes incorrectly, it returns 0 on success, 1 on illop and -EFAULT on a data access error. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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04903a30a3
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5fad293bcb
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@ -535,34 +535,40 @@ static void emulate_single_step(struct pt_regs *regs)
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}
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}
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}
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}
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static void parse_fpe(struct pt_regs *regs)
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static inline int __parse_fpscr(unsigned long fpscr)
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{
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{
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int code = 0;
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int ret = 0;
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unsigned long fpscr;
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flush_fp_to_thread(current);
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fpscr = current->thread.fpscr.val;
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/* Invalid operation */
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/* Invalid operation */
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if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
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if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
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code = FPE_FLTINV;
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ret = FPE_FLTINV;
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/* Overflow */
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/* Overflow */
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else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
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else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
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code = FPE_FLTOVF;
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ret = FPE_FLTOVF;
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/* Underflow */
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/* Underflow */
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else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
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else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
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code = FPE_FLTUND;
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ret = FPE_FLTUND;
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/* Divide by zero */
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/* Divide by zero */
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else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
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else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
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code = FPE_FLTDIV;
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ret = FPE_FLTDIV;
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/* Inexact result */
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/* Inexact result */
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else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
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else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
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code = FPE_FLTRES;
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ret = FPE_FLTRES;
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return ret;
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}
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static void parse_fpe(struct pt_regs *regs)
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{
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int code = 0;
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flush_fp_to_thread(current);
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code = __parse_fpscr(current->thread.fpscr.val);
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_exception(SIGFPE, regs, code, regs->nip);
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_exception(SIGFPE, regs, code, regs->nip);
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}
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}
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@ -773,10 +779,21 @@ void __kprobes program_check_exception(struct pt_regs *regs)
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* hardware people - not sure if it can happen on any illegal
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* hardware people - not sure if it can happen on any illegal
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* instruction or only on FP instructions, whether there is a
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* instruction or only on FP instructions, whether there is a
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* pattern to occurences etc. -dgibson 31/Mar/2003 */
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* pattern to occurences etc. -dgibson 31/Mar/2003 */
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if (do_mathemu(regs) == 0) {
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switch (do_mathemu(regs)) {
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case 0:
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emulate_single_step(regs);
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emulate_single_step(regs);
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return;
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return;
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case 1: {
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int code = 0;
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code = __parse_fpscr(current->thread.fpscr.val);
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_exception(SIGFPE, regs, code, regs->nip);
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return;
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}
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case -EFAULT:
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_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
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return;
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}
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}
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/* fall through on any other errors */
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#endif /* CONFIG_MATH_EMULATION */
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#endif /* CONFIG_MATH_EMULATION */
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/* Try to emulate it if we should. */
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/* Try to emulate it if we should. */
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@ -892,18 +909,39 @@ void SoftwareEmulation(struct pt_regs *regs)
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#ifdef CONFIG_MATH_EMULATION
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#ifdef CONFIG_MATH_EMULATION
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errcode = do_mathemu(regs);
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errcode = do_mathemu(regs);
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switch (errcode) {
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case 0:
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emulate_single_step(regs);
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return;
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case 1: {
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int code = 0;
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code = __parse_fpscr(current->thread.fpscr.val);
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_exception(SIGFPE, regs, code, regs->nip);
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return;
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}
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case -EFAULT:
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_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
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return;
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default:
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_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
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return;
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}
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#else
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#else
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errcode = Soft_emulate_8xx(regs);
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errcode = Soft_emulate_8xx(regs);
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#endif
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switch (errcode) {
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if (errcode) {
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case 0:
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if (errcode > 0)
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_exception(SIGFPE, regs, 0, 0);
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else if (errcode == -EFAULT)
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_exception(SIGSEGV, regs, 0, 0);
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else
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_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
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} else
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emulate_single_step(regs);
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emulate_single_step(regs);
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return;
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case 1:
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_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
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return;
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case -EFAULT:
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_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
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return;
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}
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#endif
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}
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}
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#endif /* CONFIG_8xx */
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#endif /* CONFIG_8xx */
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