MIPS: BCM63XX: Add register and IRQ definitions for USB 2.0 device
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4084/ Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Kevin Cernekee
John Crispin
Родитель
a56e853805
Коммит
5fd66c2b2b
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@ -120,6 +120,8 @@ enum bcm63xx_regs_set {
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RSET_OHCI0,
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RSET_OHCI_PRIV,
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RSET_USBH_PRIV,
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RSET_USBD,
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RSET_USBDMA,
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RSET_MPI,
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RSET_PCMCIA,
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RSET_PCIE,
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@ -162,6 +164,8 @@ enum bcm63xx_regs_set {
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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#define RSET_EHCI_SIZE 256
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#define RSET_USBD_SIZE 256
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#define RSET_USBDMA_SIZE 1280
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#define RSET_PCMCIA_SIZE 12
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#define RSET_M2M_SIZE 256
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#define RSET_ATM_SIZE 4096
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@ -183,10 +187,11 @@ enum bcm63xx_regs_set {
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#define BCM_6328_GPIO_BASE (0xb0000080)
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#define BCM_6328_SPI_BASE (0xdeadbeef)
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#define BCM_6328_UDC0_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xb000c000)
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#define BCM_6328_OHCI0_BASE (0xb0002600)
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#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_USBH_PRIV_BASE (0xb0002700)
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#define BCM_6328_USBD_BASE (0xb0002400)
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#define BCM_6328_MPI_BASE (0xdeadbeef)
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#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6328_PCIE_BASE (0xb0e40000)
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@ -232,6 +237,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_OHCI0_BASE (0xdeadbeef)
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#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
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#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6338_USBD_BASE (0xdeadbeef)
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#define BCM_6338_MPI_BASE (0xfffe3160)
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#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6338_PCIE_BASE (0xdeadbeef)
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@ -286,6 +292,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6345_USBD_BASE (0xdeadbeef)
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#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
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#define BCM_6345_DSL_BASE (0xdeadbeef)
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#define BCM_6345_UBUS_BASE (0xdeadbeef)
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@ -319,9 +326,11 @@ enum bcm63xx_regs_set {
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_USBDMA_BASE (0xdeadbeef)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
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#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6348_USBD_BASE (0xdeadbeef)
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#define BCM_6348_MPI_BASE (0xfffe2000)
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#define BCM_6348_PCMCIA_BASE (0xfffe2054)
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#define BCM_6348_PCIE_BASE (0xdeadbeef)
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@ -362,9 +371,11 @@ enum bcm63xx_regs_set {
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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#define BCM_6358_SPI_BASE (0xfffe0800)
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#define BCM_6358_UDC0_BASE (0xfffe0800)
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#define BCM_6358_USBDMA_BASE (0xdeadbeef)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
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#define BCM_6358_USBD_BASE (0xdeadbeef)
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#define BCM_6358_MPI_BASE (0xfffe1000)
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#define BCM_6358_PCMCIA_BASE (0xfffe1054)
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#define BCM_6358_PCIE_BASE (0xdeadbeef)
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@ -406,9 +417,11 @@ enum bcm63xx_regs_set {
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#define BCM_6368_GPIO_BASE (0xb0000080)
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#define BCM_6368_SPI_BASE (0xb0000800)
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#define BCM_6368_UDC0_BASE (0xdeadbeef)
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#define BCM_6368_USBDMA_BASE (0xb0004800)
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#define BCM_6368_OHCI0_BASE (0xb0001600)
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#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
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#define BCM_6368_USBD_BASE (0xb0001400)
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#define BCM_6368_MPI_BASE (0xb0001000)
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#define BCM_6368_PCMCIA_BASE (0xb0001054)
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#define BCM_6368_PCIE_BASE (0xdeadbeef)
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@ -458,6 +471,8 @@ extern const unsigned long *bcm63xx_regs_base;
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__GEN_RSET_BASE(__cpu, OHCI0) \
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__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
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__GEN_RSET_BASE(__cpu, USBH_PRIV) \
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__GEN_RSET_BASE(__cpu, USBD) \
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__GEN_RSET_BASE(__cpu, USBDMA) \
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__GEN_RSET_BASE(__cpu, MPI) \
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__GEN_RSET_BASE(__cpu, PCMCIA) \
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__GEN_RSET_BASE(__cpu, PCIE) \
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@ -499,6 +514,8 @@ extern const unsigned long *bcm63xx_regs_base;
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[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
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[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
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[RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
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[RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \
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[RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \
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[RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
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[RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
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[RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
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@ -569,6 +586,13 @@ enum bcm63xx_irq {
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IRQ_ENET_PHY,
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IRQ_OHCI0,
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IRQ_EHCI0,
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IRQ_USBD,
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IRQ_USBD_RXDMA0,
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IRQ_USBD_TXDMA0,
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IRQ_USBD_RXDMA1,
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IRQ_USBD_TXDMA1,
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IRQ_USBD_RXDMA2,
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IRQ_USBD_TXDMA2,
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IRQ_ENET0_RXDMA,
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IRQ_ENET0_TXDMA,
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IRQ_ENET1_RXDMA,
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@ -604,6 +628,13 @@ enum bcm63xx_irq {
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#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
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#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
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#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
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#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6328_PCMCIA_IRQ 0
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#define BCM_6328_ENET0_RXDMA_IRQ 0
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#define BCM_6328_ENET0_TXDMA_IRQ 0
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@ -642,6 +673,13 @@ enum bcm63xx_irq {
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#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6338_OHCI0_IRQ 0
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#define BCM_6338_EHCI0_IRQ 0
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#define BCM_6338_USBD_IRQ 0
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#define BCM_6338_USBD_RXDMA0_IRQ 0
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#define BCM_6338_USBD_TXDMA0_IRQ 0
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#define BCM_6338_USBD_RXDMA1_IRQ 0
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#define BCM_6338_USBD_TXDMA1_IRQ 0
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#define BCM_6338_USBD_RXDMA2_IRQ 0
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#define BCM_6338_USBD_TXDMA2_IRQ 0
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#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
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#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
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#define BCM_6338_ENET1_RXDMA_IRQ 0
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@ -673,6 +711,13 @@ enum bcm63xx_irq {
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#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6345_OHCI0_IRQ 0
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#define BCM_6345_EHCI0_IRQ 0
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#define BCM_6345_USBD_IRQ 0
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#define BCM_6345_USBD_RXDMA0_IRQ 0
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#define BCM_6345_USBD_TXDMA0_IRQ 0
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#define BCM_6345_USBD_RXDMA1_IRQ 0
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#define BCM_6345_USBD_TXDMA1_IRQ 0
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#define BCM_6345_USBD_RXDMA2_IRQ 0
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#define BCM_6345_USBD_TXDMA2_IRQ 0
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#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
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#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
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#define BCM_6345_ENET1_RXDMA_IRQ 0
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@ -704,6 +749,13 @@ enum bcm63xx_irq {
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#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6348_EHCI0_IRQ 0
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#define BCM_6348_USBD_IRQ 0
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#define BCM_6348_USBD_RXDMA0_IRQ 0
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#define BCM_6348_USBD_TXDMA0_IRQ 0
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#define BCM_6348_USBD_RXDMA1_IRQ 0
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#define BCM_6348_USBD_TXDMA1_IRQ 0
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#define BCM_6348_USBD_RXDMA2_IRQ 0
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#define BCM_6348_USBD_TXDMA2_IRQ 0
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#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
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#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
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#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
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@ -735,6 +787,13 @@ enum bcm63xx_irq {
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#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6358_USBD_IRQ 0
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#define BCM_6358_USBD_RXDMA0_IRQ 0
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#define BCM_6358_USBD_TXDMA0_IRQ 0
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#define BCM_6358_USBD_RXDMA1_IRQ 0
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#define BCM_6358_USBD_TXDMA1_IRQ 0
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#define BCM_6358_USBD_RXDMA2_IRQ 0
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#define BCM_6358_USBD_TXDMA2_IRQ 0
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#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
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#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
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#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
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@ -775,6 +834,13 @@ enum bcm63xx_irq {
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#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
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#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26)
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#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27)
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#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28)
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#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29)
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#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30)
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#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31)
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#define BCM_6368_PCMCIA_IRQ 0
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#define BCM_6368_ENET0_RXDMA_IRQ 0
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#define BCM_6368_ENET0_TXDMA_IRQ 0
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@ -815,6 +881,13 @@ extern const int *bcm63xx_irqs;
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[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
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[IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
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[IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
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[IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
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[IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \
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[IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \
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[IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \
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[IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \
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[IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \
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[IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \
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[IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
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[IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
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[IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
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@ -795,6 +795,12 @@
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#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
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#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
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#define USBH_PRIV_UTMI_CTL_6368_REG 0x10
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#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
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#define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
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#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
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#define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
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#define USBH_PRIV_TEST_6358_REG 0x24
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#define USBH_PRIV_TEST_6368_REG 0x14
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@ -803,6 +809,147 @@
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#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
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/*************************************************************************
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* _REG relative to RSET_USBD
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*************************************************************************/
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/* General control */
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#define USBD_CONTROL_REG 0x00
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#define USBD_CONTROL_TXZLENINS_SHIFT 14
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#define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT)
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#define USBD_CONTROL_AUTO_CSRS_SHIFT 13
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#define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
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#define USBD_CONTROL_RXZSCFG_SHIFT 12
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#define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT)
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#define USBD_CONTROL_INIT_SEL_SHIFT 8
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#define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
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#define USBD_CONTROL_FIFO_RESET_SHIFT 6
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#define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
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#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
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#define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
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#define USBD_CONTROL_DONE_CSRS_SHIFT 0
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#define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
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/* Strap options */
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#define USBD_STRAPS_REG 0x04
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#define USBD_STRAPS_APP_SELF_PWR_SHIFT 10
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#define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
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#define USBD_STRAPS_APP_DISCON_SHIFT 9
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#define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT)
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#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
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#define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
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#define USBD_STRAPS_APP_RMTWKUP_SHIFT 6
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#define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
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#define USBD_STRAPS_APP_RAM_IF_SHIFT 7
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#define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
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#define USBD_STRAPS_APP_8BITPHY_SHIFT 2
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#define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
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#define USBD_STRAPS_SPEED_SHIFT 0
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#define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT)
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/* Stall control */
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#define USBD_STALL_REG 0x08
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#define USBD_STALL_UPDATE_SHIFT 7
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#define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT)
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#define USBD_STALL_ENABLE_SHIFT 6
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#define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT)
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#define USBD_STALL_EPNUM_SHIFT 0
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#define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT)
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/* General status */
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#define USBD_STATUS_REG 0x0c
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#define USBD_STATUS_SOF_SHIFT 16
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#define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT)
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#define USBD_STATUS_SPD_SHIFT 12
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#define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT)
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#define USBD_STATUS_ALTINTF_SHIFT 8
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#define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT)
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#define USBD_STATUS_INTF_SHIFT 4
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#define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT)
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#define USBD_STATUS_CFG_SHIFT 0
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#define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT)
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/* Other events */
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#define USBD_EVENTS_REG 0x10
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#define USBD_EVENTS_USB_LINK_SHIFT 10
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#define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT)
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/* IRQ status */
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#define USBD_EVENT_IRQ_STATUS_REG 0x14
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/* IRQ level (2 bits per IRQ event) */
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#define USBD_EVENT_IRQ_CFG_HI_REG 0x18
|
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|
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#define USBD_EVENT_IRQ_CFG_LO_REG 0x1c
|
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#define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1)
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#define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
|
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#define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
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#define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
|
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|
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/* IRQ mask (1=unmasked) */
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#define USBD_EVENT_IRQ_MASK_REG 0x20
|
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|
||||
/* IRQ bits */
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||||
#define USBD_EVENT_IRQ_USB_LINK 10
|
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#define USBD_EVENT_IRQ_SETCFG 9
|
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#define USBD_EVENT_IRQ_SETINTF 8
|
||||
#define USBD_EVENT_IRQ_ERRATIC_ERR 7
|
||||
#define USBD_EVENT_IRQ_SET_CSRS 6
|
||||
#define USBD_EVENT_IRQ_SUSPEND 5
|
||||
#define USBD_EVENT_IRQ_EARLY_SUSPEND 4
|
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#define USBD_EVENT_IRQ_SOF 3
|
||||
#define USBD_EVENT_IRQ_ENUM_ON 2
|
||||
#define USBD_EVENT_IRQ_SETUP 1
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||||
#define USBD_EVENT_IRQ_USB_RESET 0
|
||||
|
||||
/* TX FIFO partitioning */
|
||||
#define USBD_TXFIFO_CONFIG_REG 0x40
|
||||
#define USBD_TXFIFO_CONFIG_END_SHIFT 16
|
||||
#define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
|
||||
#define USBD_TXFIFO_CONFIG_START_SHIFT 0
|
||||
#define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
|
||||
|
||||
/* RX FIFO partitioning */
|
||||
#define USBD_RXFIFO_CONFIG_REG 0x44
|
||||
#define USBD_RXFIFO_CONFIG_END_SHIFT 16
|
||||
#define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
|
||||
#define USBD_RXFIFO_CONFIG_START_SHIFT 0
|
||||
#define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
|
||||
|
||||
/* TX FIFO/endpoint configuration */
|
||||
#define USBD_TXFIFO_EPSIZE_REG 0x48
|
||||
|
||||
/* RX FIFO/endpoint configuration */
|
||||
#define USBD_RXFIFO_EPSIZE_REG 0x4c
|
||||
|
||||
/* Endpoint<->DMA mappings */
|
||||
#define USBD_EPNUM_TYPEMAP_REG 0x50
|
||||
#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8
|
||||
#define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
|
||||
#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
|
||||
#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
|
||||
|
||||
/* Misc per-endpoint settings */
|
||||
#define USBD_CSR_SETUPADDR_REG 0x80
|
||||
#define USBD_CSR_SETUPADDR_DEF 0xb550
|
||||
|
||||
#define USBD_CSR_EP_REG(x) (0x84 + (x) * 4)
|
||||
#define USBD_CSR_EP_MAXPKT_SHIFT 19
|
||||
#define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
|
||||
#define USBD_CSR_EP_ALTIFACE_SHIFT 15
|
||||
#define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
|
||||
#define USBD_CSR_EP_IFACE_SHIFT 11
|
||||
#define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT)
|
||||
#define USBD_CSR_EP_CFG_SHIFT 7
|
||||
#define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT)
|
||||
#define USBD_CSR_EP_TYPE_SHIFT 5
|
||||
#define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT)
|
||||
#define USBD_CSR_EP_DIR_SHIFT 4
|
||||
#define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT)
|
||||
#define USBD_CSR_EP_LOG_SHIFT 0
|
||||
#define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_MPI
|
||||
|
|
|
|||
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